Xilinx Virtex-4 FX FPGA, User Manual

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ML42 x User Guide www.xilinx.com 29
UG087 (v1.3) May 30, 2008
Detailed Description
R
20. RS-232 Port
The RS-232 port pins are as shown in Table 22 . The pins are set up in DTE mode as shown
in Figure 3 .
21. External Bias Potentiometers (RTERM)
Each Virtex-4 FPGA MGT column has two external pins that can be used to control internal
bias currents and voltages in the analog section of the MGT known as the PMA (Physical
Media Attachment). The external bias potentiometers are labeled RTERM 105 and RTERM
110. Through a master/slave bias circuit, these externally controlled biases can be shared
across all MGT tiles within the MGT column. For more information on Rocket IO external
biasing, see the
Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide [Ref 1] .
Table 22: RS-232 Port Pins
FPGA UART
Port Name
Direction Port Name ML421 ML423 ML424
TXD OUT T1IN G16 E16 M25
RTS OUT T2IN G15 F16 N24
CTS IN R2OUT H11 F13 G15
RXD IN R1OUT J11 G13 H15
Figure 3: RS-232 Pins in DTE Mode
UG0 8 7_0 3 _062205
R S -2 3 2 DB9 Virtex-4
U1 U2 J52
T1IN
TXD
RT S
RXD
CT S
Pin 3
Pin 7
Pin 2
Pin 8
T2IN
R1OUT
R2OUT
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