Xilinx VIODC, User Manual

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UG235 (v1.2.1) October 31, 2007
Chapter 6: SDI Interface
R
Table 6-1 shows the various frequencies produced by the PLL502 and ICS664-02 when
configured for the three different SDI bit rates. In SD-SDI mode, the 54 MHz clock out of
the ICS664-02 is multiplied by two by a Digital Clock Manager (DCM) to produce the
108 MHz reference clock needed by the RocketIO transceiver in the SDI receiver.
SDI Receiver
Figure 6-1 is a block diagram of the SDI receiver. Shaded blocks in the figure are external to
the FPGA.
The serial bitstream enters the RocketIO receiver after passing through an SDI cable
equalizer. The RocketIO receiver must be give a reference clock of the appropriate
frequency depending on the bit rate being received. If the reference clock frequency
doesn’t match the bit rate of the input bitstream the receiver will not lock to the bitstream.
If the demo is in Auto Rx mode, the automatic rate detection logic will sequence the
RocketIO receiver through the three different bit rates supported by the demo until the
receiver locks.
1. It is possible to use 108 MHz instead of 54 MHz for SD-SDI in the transmitter. However, because the ICS664-
02 cannot directly generate 108 MHz, a DCM would be required to generate the 108 MHz clock resulting in
more jitter on the output of the SDI transmitter due to higher jitter on the reference clock. The receiver section
requires 108 MHz and cannot get by with 54 MHz. However, jitter on the RocketIO reference clock is not as
important for the receiver.
Table 6-1: RocketIO Reference Clock Generation
Bit Rate
VCXO
Frequency
ICS664-02 Frequency Rx REFCLK Tx REFCLK
1.485 Gb/s 13.5 MHz 74.25 MHz 74.25 MHz 74.25 MHz
1.4835 Gb/s 13.5 MHz 74.1758 MHz 74.1758 MHz 74.1758 MHz
270 Mb/s 54 MHz 54 MHz 108 MHz 54 MHz
Figure 6-1: SDI Receiver Block Diagram
Cable
Equalizer
SDI In
ICS664-02
DCM
hd_sd
RXN
RXP
REFCLK2
REFCLKSEL
REFCLK
RXUSRCLK
RXUSRCLK2
RocketIO
RXRECCLK
RXDATA
108 MHz
74.25 MHz or
74.1758 MHz
BUFG
HD-SDI
Descrambler
HD-SDI
Framer
Y
C
20 20
10
10
SD-SDI
Data
Recovery
10 SD-SDI
Descrambler
SD-SDI
Framer
10 EDH
Checker
10
CRC Check
27 MHz Clock Enable
AutoRate
Detection
freq control
10
hd_sd
SD
Analog
Video
HD
Analog
Video
Demo Mode
Control
From ML402
DIP switches
hd_sd
freq control
Y
C
clk
S
AD
V7321B
ug235_ch5_01_111405
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