Xilinx VCU110, User Manual

Page: 93 / 156

VCU110 Evaluation Board www.xilinx.com 93
UG1073 (v1.2) March 26, 2016
Chapter 1: VCU110 Evaluation Board Features
GPIO DIP Switch
[ Figure 1-2 , callout 26]
Figure 1-21 shows the GPIO DIP switch circuit.
Table 1-49 lists the GPIO Connections to FPGA U1.
X-Ref Target - Figure 1-21
Figure 1-21: CPU GPIO DIP Switch
Table 1-49: VCU110 GPIO Connections to FPGA U1
FPGA Pin (U1) Schematic Net Name I/O Standard GPIO
GPIO LEDs (Active-High)
(1)
N25 GPIO_LED_0 LVCMOS12 DS7.1
N22 GPIO_LED_1 LVCMOS12 DS6.1
M22 GPIO_LED_2 LVCMOS12 DS8.1
M26 GPIO_LED_3 LVCMOS12 DS9.1
M25 GPIO_LED_4 LVCMOS12 DS10.1
P24 GPIO_LED_5 LVCMOS12 DS33.1
N24 GPIO_LED_6 LVCMOS12 DS32.1
N23 GPIO_LED_7 LVCMOS12 DS31.1
Directional Pushbuttons (Active-High)
AT11 GPIO_SW_N LVCMOS18 SW10.3
AY13 GPIO_SW_E LVCMOS18 SW9.3
AM16 GPIO_SW_W LVCMOS18 SW6.3
BC16 GPIO_SW_S LVCMOS18 SW8.3
GND
SW12
SDA04H1SBD
8
7
6
5 4
3
2
1
GPIO_DIP_SW2
GPIO_DIP_SW3
GPIO_DIP_SW1
GPIO_DIP_SW0
VCC1V2_FPGA
R40
4.70KΩ
1%
1
2
1%
4.70KΩ
R41
1
2
1%
4.70KΩ
R50
1
2
R51
4.70KΩ
1%
1
2
1/16W
1/16W
1/16W
1/16W
;
Send Feedback