Xilinx VCU110, User Manual

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VCU110 Evaluation Board www.xilinx.com 85
UG1073 (v1.2) March 26, 2016
Chapter 1: VCU110 Evaluation Board Features
The dual UART interface connections are split between two components:
• UART1 SCI 4-wire interface is connected to the XCVU190 U1 FPGA
• UART2 ECI 2-wire interface is connected to the XC7Z010 U111 Zynq SoC system
controller
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer.
These drivers permit the CP2105GM dual USB-to-UART bridge to appear as a pair of COM
ports to communications application software (for example, TeraTerm or HyperTerm) that
runs on the host computer. The VCP device drivers must be installed on the host PC prior to
establishing communications with the VCU110 evaluation board. The driver assigns the
lower PC COM port number to UART2 and the higher PC COM port number to UART1.
Table 1-46 lists the dual-UART U34 connections to FPGA U1 and system controller U111.
For more technical information on the CP2105GM and the VCP drivers, visit the Silicon Labs
website [Ref 26] .
Xilinx UART IP is expected to be implemented in the FPGA logic using IP like the LogiCORE
IP AXI UART Lite v2.0 Product Guide for Vivado Design Suite (PG142) [Ref 10] .
I2C Bus, Topology and Bus Switches
[ Figure 1-2 , callouts 21, 22]
The VCU110 evaluation board implements a 2-to-1 I2C bus arrangement. A single I2C bus
from each of the FPGA U1 XCVU190 (IIC_MAIN_SCL/SDA_LS) and system controller Zynq AP
SoC U111 (SYSCTLR_I2C_SCL/SDA) are wired to the same I2C bus through level-shifters
(FPGA U1 is wired through level-shifter U77 and system controller U111 is wired through
level-shifter U108). The output sides of U77 and U108 are wired in parallel to a common I2C
bus (IIC_SDA and _SCL_MAIN). This common I2C bus is then routed to a pair of bus switches,
a TI TCA9548 1-to-8 channel I2C bus switch (U28) and a TI PCA9544 1-to-4 channel I2C bus
switch (U80). The bus switches can operate at speeds up to 400 kHz.
Table 1-46: FPGA U1 to CP2105GM U34 Connections
FPGA U1 Pin Function Direction I/O Standard Schematic Net Name
CP2105GM Device (U34)
Pin Function Direction
AR20 Receive Input LVCMOS18 USB_UART_TX 21
Transmit
data
Output
AT20 Transmit Output LVCMOS18 USB_UART_RX 20
Receive
data
Input
AR19
Clear to
send
Output LVCMOS18 USB_UART_CTS 18
Clear to
send
Input
AU19
Request
to send
Input LVCMOS18 USB_UART_RTS 19
Request
to send
Output
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