Xilinx VCU110, User Manual

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VCU110 Evaluation Board www.xilinx.com 83
UG1073 (v1.2) March 26, 2016
Chapter 1: VCU110 Evaluation Board Features
Table 1-45 details the FPGA U1 to U58 M88E111 Ethernet PHY connections.
Table 1-45:
FPGA U1 to Ethernet PHY U58 Connections
FPGA (U1) Pin Net Name I/O Standard
M88E111 PHY U58
Pin Name
BB21 PHY_MDIO LVCMOS18 M1 MDIO_SDA
BC18 PHY_MDC LVCMOS18 L3 MDC_SCL
BC21 PHY_INT LVCMOS18 L1 INT_B
BB18 PHY_RESET LVCMOS18 K3 RESET_B
Notes:
1. Ethernet PHY U58 signals are level-shifted (U45) to 1.8V for interface to FPGA U1 Bank 84.
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