Xilinx VCU110, User Manual

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VCU110 Evaluation Board www.xilinx.com 63
UG1073 (v1.2) March 26, 2016
Chapter 1: VCU110 Evaluation Board Features
Quad 232:
• REFCLK0 - not connected
• REFCLK1 - not connected
• Four GTH transceivers allocated to HMC_L0 TX and RX[12:15]_P/N (U160)
Quad 233:
• REFCLK0 - PCIE_CABLE_CLK_C_P/N (J136)
• REFCLK1 - not connected
• Four GTH transceivers allocated to PCIE_CABLE_TX and RX[0:3]_P/N (J136)
Table 1-26 through Table 1-38 list the VCU110 FPGA U1 GTH Quads 220-222 and 224-233
connections, respectively.
Table 1-26: VCU110 FPGA U1 GTH Quad 220 Connections
FPGA (U1) Pin Name
FPGA
(U1) Pin
Schematic Net Name
(1)
Connected
Pin Number
Connected Pin
Name
Connected
Device
MGTHTXP0_220 BF9 FMC_HPC0_DP0_C2M_P C2 DP0_C2M_P
FMC HPC0
J22
MGTHTXN0_220 BF8 FMC_HPC0_DP0_C2M_N C3 DP0_C2M_N
MGTHRXP0_220 BF14 FMC_HPC0_DP0_M2C_P C6 DP0_M2C_P
MGTHRXN0_220 BF13 FMC_HPC0_DP0_M2C_N C7 DP0_M2C_N
MGTHTXP1_220 BE11 FMC_HPC0_DP1_C2M_P A22 DP1_C2M_P
MGTHTXN1_220 BE10 FMC_HPC0_DP1_C2M_N A23 DP1_C2M_N
MGTHRXP1_220 BD14 FMC_HPC0_DP1_M2C_P A2 DP1_M2C_P
MGTHRXN1_220 BD13 FMC_HPC0_DP1_M2C_N A3 DP1_M2C_N
MGTHTXP2_220 BE7 FMC_HPC0_DP2_C2M_P A26 DP2_C2M_P
MGTHTXN2_220 BE6 FMC_HPC0_DP2_C2M_N A27 DP2_C2M_N
MGTHRXP2_220 BF4 FMC_HPC0_DP2_M2C_P A6 DP2_M2C_P
MGTHRXN2_220 BF3 FMC_HPC0_DP2_M2C_N A7 DP2_M2C_N
MGTHTXP3_220 BD9 FMC_HPC0_DP3_C2M_P A30 DP3_C2M_P
MGTHTXN3_220 BD8 FMC_HPC0_DP3_C2M_N A31 DP3_C2M_N
MGTHRXP3_220 BD4 FMC_HPC0_DP3_M2C_P A10 DP3_M2C_P
MGTHRXN3_220 BD3 FMC_HPC0_DP3_M2C_N A11 DP3_M2C_N
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