Xilinx VCU110, User Manual

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VCU110 Evaluation Board www.xilinx.com 114
UG1073 (v1.2) March 26, 2016
Chapter 1: VCU110 Evaluation Board Features
Table 1-59: J22 VITA 57.1 FMC HPC0 Sections G and H to FPGA U1 Connections
J22
FMC
HPC0
Pin
Schematic
Net Name
I/O
Standard
U1
FPGA
Pin
J22
FMC
HPC0
Pin
Schematic
Net Name
I/O
Standard
U1 FPGA
Pin
G2 NA NA H1 FMC_HPC0_VREF_A_M2C
(3)
NA
G3 NA NA H2 FMC_HPC0_PRSNT_M2C_B
(1)(2)
LVCMOS18 R13
G6 FMC_HPC0_LA00_CC_P LVDS AY34 H4 FMC_HPC0_CLK0_M2C_P LVDS AW33
G7 FMC_HPC0_LA00_CC_N LVDS AY35 H5 FMC_HPC0_CLK0_M2C_N LVDS
AY33
G9 FMC_HPC0_LA03_P LVDS BA34 H7 FMC_HPC0_LA02_P LVDS
BA36
G10 FMC_HPC0_LA03_N LVDS BB34 H8 FMC_HPC0_LA02_N LVDS BB36
G12 FMC_HPC0_LA08_P LVDS BE29 H10 FMC_HPC0_LA04_P LVDS BB32
G13 FMC_HPC0_LA08_N LVDS BF29 H11 FMC_HPC0_LA04_N LVDS
BB33
G15 NA NA H13 FMC_HPC0_LA07_P LVDS
BA31
G16 NA NA H14 FMC_HPC0_LA07_N LVDS BB31
G18 NA NA H16 NA NA
G19 NA NA H17 NA NA
G21 NA NA H19 NA NA
G22 NA NA H20 NA NA
G24 NA NA H22 NA NA
G25 NA NA H23 NA NA
G27 NA NA H25 NA NA
G28 NA NA H26 NA NA
G30 NA NA H28 NA NA
G31 NA NA H29 NA NA
G33 NA NA H31 NA NA
G34 NA NA H32 NA NA
G36 NA NA H34 NA NA
G37 NA NA H35 NA NA
G39 VADJ _1V8_FPGA H37 NA NA
H38 NA NA
H40 VADJ _1V8_FPGA
Notes:
1. FMC_HPC0_PRSNT_M2C_B level-shifted from 3.3V to 1.8V at U44.
2. FMC_HPC0_PRSNT_M2C_B level-shifted from 3.3V to 1.8V at TXS0108E U109, connected to U111 pin R13.
3. FMC_HPC0_VREF_A_M2C is the source of U1 bank 68 Vref pin AM32 connected via DNP series resistor R1674, and U1 bank
84 Vref pin AM17 via DNP resistor R796.
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