Xilinx VCU110, User Manual

Page: 103 / 156

VCU110 Evaluation Board www.xilinx.com 103
UG1073 (v1.2) March 26, 2016
Chapter 1: VCU110 Evaluation Board Features
PCIe cable connector J136 connections are detailed in Table 1-53 .
For additional information about UltraScale PCIe functionality, see LogiCORE IP UltraScale
FPGAs Gen3 Integrated Block for PCI Express v1.0 Product Guide for Vivado Design Suite
(PG156) [Ref 8] . See [Ref 27] for additional information about the PCI Express® standard.
Table 1-53: VCU110 PCIe Cable Conn. J136 to FPGA U1 Connections GTH Quad 233
FPGA (U1) Pin Name
FPGA
(U1) Pin
Schematic Net Name
(1)
Connected
Pin Number
Connected Pin
Name
Connected
Device
MGTHTXP0_233 D9 PCIE_CABLE_TX3_C_P
(2)
A11 PETP3
PCIe cable
connector J136
MGTHTXN0_233 D8 PCIE_CABLE_TX3_C_N
(2)
A12 PETN3
MGTHRXP0_233 D14 PCIE_CABLE_RX3_P B11 PERP3
MGTHRXN0_233 D13 PCIE_CABLE_RX3_N B12 PERN3
MGTHTXP1_233 C11 PCIE_CABLE_TX2_C_P
(2)
A8 PETP2
MGTHTXN1_233 C10 PCIE_CABLE_TX2_C_N
(2)
A9 PETN2
MGTHRXP1_233 C16 PCIE_CABLE_RX2_P B8 PERP2
MGTHRXN1_233 C15 PCIE_CABLE_RX2_N B9 PERN2
MGTHTXP2_233 B9 PCIE_CABLE_TX1_C_P
(2)
A5 PETP1
MGTHTXN2_233 B8 PCIE_CABLE_TX1_C_N
(2)
A6 PETN1
MGTHRXP2_233 B14 PCIE_CABLE_RX1_P B5 PERP1
MGTHRXN2_233 B13 PCIE_CABLE_RX1_N B6 PERN1
MGTHTXP3_233 A11 PCIE_CABLE_TX0_C_P
(2)
A2 PETP0
MGTHTXN3_233 A10 PCIE_CABLE_TX0_C_N
(2)
A3 PETN0
MGTHRXP3_233 A16 PCIE_CABLE_RX0_P B2 PERP0
MGTHRXN3_233 A15 PCIE_CABLE_RX0_N B3 PERN0
MGTREFCLK0P_233 J11 PCIE_CABLE_CLK_C_P
(2)
A14 CREFCLKP
MGTREFCLK0N_233 J10 PCIE_CABLE_CLK_C_N
(2)
A15 CREFCLKN
Notes:
1. MGT connections I/O standard not applicable.
2. Series capacitor coupled.
Send Feedback