Xilinx VC7203, User Manual

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18 www.xilinx.com VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012
Chapter 1: VC7203 Board Features and Operation
200 MHz 2.5V LVDS Oscillator
U35 (callout 11 , Figure 1-2 ).
The VC7203 board has one 200 MHz 2.5V LVDS oscillator (U35) connected to multi-region
clock capable (MRCC) inputs on the FPGA.
Table 1-7 lists the FPGA pin connections to the
LVDS oscillator.
Differential SMA MRCC Pin Inputs
Callout 30 , Figure 1-2 .
The VC7203 board provides two pairs of differential SMA transceiver clock inputs that can
be used for connecting to an external function generator. The FPGA MRCC pins are
connected to the SMA connectors as shown in
Table 1-8 .
SuperClock-2 Module
Callout 10 , Figure 1-2 .
The SuperClock-2 module connects to the clock module interface connector (J82) and
provides a programmable, low-noise and low-jitter clock source for the VC7203 board. The
clock module maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock
pair, and 1 reset pin.
Table 1-9 shows the FPGA I/O mapping for the SuperClock-2 module
2 ON OFF ON
3 ON OFF OFF
4 OFF ON ON
5 OFF ON OFF
6 OFF OFF ON
7 OFF OFF OFF
Table 1-6: SW8 DIP Switch Configuration (Cont’d)
Configuration Bitstream
Address
ADR2 ADR1 ADR0
Table 1-7: LVDS Oscillator MRCC Connections
U1 FPGA Pin Net Name U35 Pin
E19 IO_LVDS_OSC_P 4
E18 IO_LVDS_OSC_N 5
Table 1-8: Differential SMA Clock Connections
U1 FPGA Pin Net Name SMA Connector
H19 CLK_DIFF_1_P J99
G18 CLK_DIFF_1_N J100
K39 CLK_DIFF_2_P J98
K40 CLK_DIFF_2_N J101