Xilinx VC709, User Manual

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52 www.xilinx.com VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
Chapter 1: VC709 Evaluation Board Features
• 10 GTH transceivers
• 2 GTH clocks
• 2 differential clocks
The FMC1 HPC signals are distributed across GTH Quads 117, 118, and 119.
The VC709 board VADJ voltage for the FMC1 HPC (J35) connector is fixed at 1.8V.
Signaling speed ratings:
• Single-ended: 9 GHz (18 Gb/s)
• Differential
• Optimal vertical: 9 GHz (18 Gb/s)
• Optimal horizontal: 16 GHz (32 Gb/s)
• High Density Vertical: 7 GHz (15 Gb/s)
Mechanical specifications:
• Samtec SEAM/SEAF Series
• 1.27 mm x 1.27 mm (0.050-inch x 0.050-inch) pitch
The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on
a –3 dB insertion loss point within a two-level signaling environment.
Table 1-20 shows the FMC HPC connector J35 connections to FPGA U1.
Table 1-20: VITA 57.1 FMC HPC J35 Connections to FPGA U1
J35 FMC
HPC Pin
Schematic Net Name U1 FPGA Pin
J64 FMC
HPC Pin
Schematic Net Name
U1 FPGA
Pin
A2 FMC1_HPC_DP1_M2C_P C6 B1 NC NA
A3 FMC1_HPC_DP1_M2C_N C5 B4 FMC1_HPC_DP9_M2C_P N6
A6 FMC1_HPC_DP2_M2C_P B8 B5 FMC1_HPC_DP9_M2C_N N5
A7 FMC1_HPC_DP2_M2C_N B7 B8 FMC1_HPC_DP8_M2C_P P8
A10 FMC1_HPC_DP3_M2C_P A6 B9 FMC1_HPC_DP8_M2C_N P7
A11 FMC1_HPC_DP3_M2C_N A5 B12 FMC1_HPC_DP7_M2C_P E6
A14 FMC1_HPC_DP4_M2C_P H8 B13 FMC1_HPC_DP7_M2C_N E5
A15 FMC1_HPC_DP4_M2C_N H7 B16 FMC1_HPC_DP6_M2C_P F8
A18 FMC1_HPC_DP5_M2C_P G6 B17 FMC1_HPC_DP6_M2C_N F7
A19 FMC1_HPC_DP5_M2C_N G5 B20 FMC1_HPC_GBTCLK1_M2C_P E10
A22 FMC1_HPC_DP1_C2M_P D4 B21 FMC1_HPC_GBTCLK1_M2C_N E9
A23 FMC1_HPC_DP1_C2M_N D3 B24 FMC1_HPC_DP9_C2M_P M4
A26 FMC1_HPC_DP2_C2M_P C2 B25 FMC1_HPC_DP9_C2M_N M3
A27 FMC1_HPC_DP2_C2M_N C1 B28 FMC1_HPC_DP8_C2M_P N2
A30 FMC1_HPC_DP3_C2M_P B4 B29 FMC1_HPC_DP8_C2M_N N1
A31 FMC1_HPC_DP3_C2M_N B3 B32 FMC1_HPC_DP7_C2M_P F4
A34 FMC1_HPC_DP4_C2M_P J2 B33 FMC1_HPC_DP7_C2M_N F3