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Common Options in Block Parameters Dialog Box

19

Xilinx Blockset Overview

Xilinx LogiCORE



Versions

The Xilinx LogiCORE



blocks (indicating the version numbers being supported by

the System Generator) used in Xilinx System Generator v2.1 are listed below.

Common Options in Block Parameters Dialog Box

Each Xilinx block has several configurable parameters, seen in the block parameters
dialog box. Many of these parameters are specific to that particular block. Those block

Xilinx Block

Xilinx LogiCORE

Version

Accumulator

ACCUMULATOR

V5.0

Addressable Shift
Register

RAM_SHIFT

V5.0

Adder/Subtractor

ADDSUB

V5.0

CIC

CIC

V1.0

Counter

BINARY_COUNTER

V5.0

Constant Multiplier

MULT_GEN

V4.0

Convolutional
Encoder

CONVOLUTION

V1.0

DDS

DDS

V4.0

Dual Port Ram

MEM_DP_BLOCK

V3.2

FIFO

SYNC_FIFO

V3.0

FFT

FFT and MEM_DP_BLOCK

V1.0 (Virtex, Spartan-II),
V2.0 (Virtex-II)
V3.2 (MEM_DP_BLOCK)

FIR Filter

DA_FIR

V6.0

Interleaver/
Deinterleaver

INTERLEAVER

V1.1

Inverter

GATE_BUS

V5.0

Logical

GATE_BUS

V5.0

Multiplier (mult)

MULT_GEN

V4.0

Mutiplexer (mux)

BUS_MUX

V5.0

Negate

TWOS_COMP

V5.0

Relational

COMPARE

V5.0

RS Decoder

RS_DECODER

V2.0

RS Encoder

RS_ENCODER

V2.0

Sine Cosine

SIN_COS

V3.0

Single Port RAM

MEM_SP_BLOCK and

DIST_MEM

V3.2(BRAM), V5.0 (dist.)

State Machines

MEM_SP_BLOCK and

DIST_MEM

V3.2(BRAM), V5.0 (dist.)

ROM

MEM_SP_BLOCK and

DIST_MEM

V3.2 (BRAM), V5.0 (dist.)

Viterbi Decoder

VITERBI

V1.0

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Summary of Contents for System Generator V2.1

Page 1: ...A Xilinx System Generator v2 1 for Simulink User Guide Xilinx Blockset Reference Guide Introduction Xilinx Blockset Overview Xilinx Blocks System Generator Software Features Using the Xilinx Software...

Page 2: ...e Chapter 3 Xilinx Blocks describes the details of each block including options and use of Xilinx LogiCOREs This chapter also tells where to find descriptions of the cores on your computer Chapter 4 S...

Page 3: ...he Xilinx design environment http support xilinx com xlnx xil_tt_home jsp Tutorials Tutorials covering Xilinx ISE 4 1i design flows from design entry to verification and debugging http support xilinx...

Page 4: ...de 100 Courier bold indicates literal commands that you enter in a command line prompt or dialog box However triangular braces in Courier bold are not literal cd your MATLAB home directory Italic font...

Page 5: ...Xilinx Blocks within a Simulink Model 16 The Block Parameters Dialog Box 16 The Nature of Signals in the Xilinx Blockset 16 Use of Xilinx Smart IP Cores by the System Generator 18 Licensed Cores 18 X...

Page 6: ...Set Valid Bit 45 Slice 45 Sync 47 Up Sample 50 Communication 52 Convolutional Encoder 52 Depuncture 54 Interleaver Deinterleaver 55 Puncture 58 RS Decoder 59 RS Encoder 63 Viterbi Decoder 68 DSP 70 CI...

Page 7: ...Tips for creating a high performance design 132 Using the System Generator Constraints Files 133 System Clock Period 133 Multicycle Path Constraints 133 IOB Timing and Placement Constraints 134 Exampl...

Page 8: ...nting highly parallel arithmetic architectures this makes the FPGA ideally suited for creating high performance custom data path processors for tasks such as digital filtering fast Fourier transforms...

Page 9: ...tically to fit gracefully into a system level framework For example although the underlying IP blocks operate on unsigned integers System Generator allows signed and unsigned fixed point numbers to be...

Page 10: ...g dynamical systems System Generator consists of a Simulink library called the Xilinx Blockset and software to translate a Simulink model into a hardware realization of the model System Generator maps...

Page 11: ...to choose the target FPGA device target system clock period and other implementation options System Generator translates the Simulink model into a hardware realization by mapping Xilinx Blockset eleme...

Page 12: ...converts to fixed point incrementally At all times these three representations can be freely intermingled without any changes to the signal flow graph This mixing is possible because library building...

Page 13: ...at can be used to achieve hardware handshakes between blocks For example upon startup a pipeline may define its output invalid until it has flushed its pipe By inspecting the valid bits of its inputs...

Page 14: ...ration For a black box instantiation the design must provide both a Simulink model and an implementation System Generator cannot automatically provide the verification that the two representations of...

Page 15: ...ulink library browser It consists of building blocks that can be instantiated within a Simulink model and like other Simulink blocksets blocks can be combined to form subsystems and arbitrary hierarch...

Page 16: ...specific parameters specific to the particular block only Double clicking on any block icon on a sheet will open its block parameters dialog box Details of the use of each block s parameters dialog c...

Page 17: ...tor This is a commonly used handshaking mechanism There are different circumstances under which the status indicator may be set to invalid For example invalid data might mean that a pipeline has not y...

Page 18: ...Box functionality you can also add HDL simulation to this flow To speed this design cycle it is possible to instruct System Generator to not invoke Xilinx CORE Generator to re generate LogiCOREs that...

Page 19: ...Subtractor ADDSUB V5 0 CIC CIC V1 0 Counter BINARY_COUNTER V5 0 Constant Multiplier MULT_GEN V4 0 Convolutional Encoder CONVOLUTION V1 0 DDS DDS V4 0 Dual Port Ram MEM_DP_BLOCK V3 2 FIFO SYNC_FIFO V3...

Page 20: ...roject directory subsequently running the Xilinx Implementation tools will produce an error If you select Implement with Xilinx Smart IP Core but do not select Generate Core you will be able to simula...

Page 21: ...nt the fractional portion of a value The Xilinx fixed point data type supports several options for user defined precision In the case of overflow the options are to saturate to the largest positive or...

Page 22: ...data samples are transmitted in double precision You can easily identify which blocks are currently set to Override with Doubles When this option is set affected Xilinx blocks are displayed in gray r...

Page 23: ...ay insert delay change the sample rate and introduce constants counters multiplexers etc The Basic Elements library also has two special blocks the System Generator and the Black Box System Generator...

Page 24: ...enerate your files in order to keep your Xilinx project files and Simulink model files directories organized separately System Clock Period Enter the desired System Clock Period of your design in nano...

Page 25: ...bsystems to selectively mask this effect For an explanation of the Override with Doubles behavior see the Common Parameters section of the previous chapter Generate Cores The Generate Cores pulldown m...

Page 26: ...block is taken from the register pointed to by the address presented on the addr port Block Interface The block interface inputs and outputs as seen on the Addressable Shift Register icon are as follo...

Page 27: ...es several rate change conditions require the use of extra hardware beyond that used by the IP core to make it compliant with the Simulink simulation output A rate change condition will be detected if...

Page 28: ...he Xilinx blocks in your design But if you include a black box that is written in Verilog HDL System Generator will produce a mixed language project A VHDL black box and a Verilog black box share the...

Page 29: ...HDL type Parameter types can be any Verilog type The black box block parameters dialog box allows you to specify multiple clocks on a black box To handle more than one clock the System Generator must...

Page 30: ...s represented by unsigned integer numbers i e two unsigned numbers with binary points at position zero The Xilinx Reinterpret block provides capabilities that can extend the functionality of the Conca...

Page 31: ...tant value of the block will appear on the block icon Sampled Constant allows a sample period to be associated with the constant ouput and inherited by blocks that the constant block drives This is us...

Page 32: ...are Output Arithmetic Type Number of Bits Binary Point Parameters defining the quantization effect and the overflow effect are Quantization Behavior Overflow Behavior The Convert block does not use a...

Page 33: ...counter The down counter calculations replace addition by subtraction The free running up or down counter can be configured to load the output of the counter with a value on the input din port by sel...

Page 34: ...ing value the number at which the counter resets A value of Inf denotes the largest representable output in the specified precision This cannot be the same as the start count Count By Value specifies...

Page 35: ...e other than zeroes Block Parameters Dialog Box The block parameters dialog box can be invoked by double clicking the icon in your Simulink model Figure 3 9 Delay block parameters dialog box Parameter...

Page 36: ...a register does not change until the clock enable is sampled i e one clock cycle later To make the hardware cycle true to the Simulink model the down sample block is implemented with the following ci...

Page 37: ...lecting Zero Initial Output you can validate the first sample with valid data of zero Otherwise an invalid data NaN will be the block s first output Other parameters used by this block are explained i...

Page 38: ...ore when checked the generated core includes relative placement information This usually results in a faster implementation The resulting floorplan is a single column with two bits per slice With this...

Page 39: ...least significant bit first or most significant bit first The following waveform illustrates the block s behavior Figure 3 14 Example of Parallel to Serial behavior This example illustrates the case...

Page 40: ...ut Bits Input width Must match size of input port Number of Output Bits Output width Must divide Number of Input Bits evenly Binary Point Output binary point location An error is reported when the num...

Page 41: ...igure 3 16 Register block parameters dialog box Parameters specific to the block are Initial Value specifies the initial value in the register Quantization of Initital Value specifies desired quantiza...

Page 42: ...binary two s complement would be translated into an output of 56 111000 in binary This block can be particularly useful in applications that combine it with the Xilinx Slice block or the Xilinx Conca...

Page 43: ...to the position supplied in the Output Binary Point parameter When unchecked the arithmetic type of the output will be unchanged from the arithmetic type of the input Output Arithmetic Type The arithe...

Page 44: ...e The Serial to Parallel block has one input and one output port The input port can be any size The output port size is indicated on the block parameters dialog box Block Parameters Dialog Box Figure...

Page 45: ...r invalid status indicator This block provides some explicit control over this handshake mechanism Block Parameters Dialog Box The block parameters dialog box can be invoked by double clicking the ico...

Page 46: ...rst three fractional bits The following diagram illustrates how to extract all but the top 16 and bottom 8 bits of the input Figure 3 21 Slice block operation Block Parameters Dialog Box The block par...

Page 47: ...r binary point Relative To specifies the bit slice position relative to the Most Significant Bit MSB Least Significant Bit LSB or Binary point of the top or the bottom of the slice Other parameters us...

Page 48: ...ario could reflect for example a CORDIC based sine generator with many pipeline stages for hardware efficiency and a simple counter based sawtooth generator The rest of the diagram shows the connectio...

Page 49: ...d Figure 3 25 Design with delay rather than Sync block The Sync block can be configured to have up to four channels and to add latency to all channels beyond the minimum required Block Parameters Dial...

Page 50: ...utput sample period is i k where i is the input sample period and k the sampling rate In Simulink a block changes its output right after it is enabled In hardware a register does not change until the...

Page 51: ...output sample period to the input and is essentially a sample rate multiplier For example a ratio of 2 indicates a doubling of the input sample rate If a non integer ratio is desired the Up Sample blo...

Page 52: ...the figure below The length of the shift register and the code s constraint length is equal to the length of the convolution codes that characterize the encoder specified in the block s parameters di...

Page 53: ...tput Length of convolution code must be between 3 and 9 inclusive Convolution Code 3 Used to generate bit 3 of the output Length of convolution code must be between 3 and 9 inclusive Other parameters...

Page 54: ...be used to decode a range of punctured convolution codes The following diagram illustrates an application of this block to implement soft decision Viterbi decoding of punctured convolution codes Figur...

Page 55: ...k implements an interleaver or a deinterleaver An interleaver is a device that rearranges the ordering of a sequence of symbols in a one to one deterministic manner Associated with any interleaver is...

Page 56: ...lock is in deinterleaver mode the input data sampled on the DIN port is multiplexed into and out of B shift registers onto the DOUT port using two synchronized commutator arms Branch 0 will have a shi...

Page 57: ...he same as the input port din Block Parameters Dialog Box Figure 3 36 Interleaver Deinterleaver block parameters dialog box Parameters specific to the block are Mode Interleaver or Deinterleaver Numbe...

Page 58: ...a of type UFixK_0 where K is equal to the number of ones in the puncture code The Xilinx Puncture block can be used to implement a range of punctured convolution codes The following diagram illustrate...

Page 59: ...inal data A Reed Solomon code is specified as RS n k with s bit symbols Reed Solomon codes are usually referred to as n k codes where n is the total number of symbols in a code block and k is the numb...

Page 60: ...ample period to mark the beginning of a codeword The start signal must be a UFix1_0 erase when erase is asserted for a particular sample period data input on the din port is marked as an erasure to be...

Page 61: ...re Custom allows you to set all the block parameters ATSC implements ATSC Advanced Television Systems Committee stan dard 207 187 shortened RS code CCSDS implements CCSDS Consultative Committee for Sp...

Page 62: ...where the 1st element corresponds to the highest degree of the polynomial A value of zero causes the default polynomial for the given symbol width to be selected The specified polynomial should be a...

Page 63: ...ods is dependent on the values of n error correcting capacity of the code and Clock Periods Per Symbol set by the block The latency of the RS decoder block is always equal to the latency returned by t...

Page 64: ...symbols of s bits each The following diagram shows a typical Reed Solomon codeword This is known as a Systematic code because the data is left unchanged and the parity symbols are appended Figure 3 4...

Page 65: ...as the first input information symbol The start signal is ignored if bypass is asserted high for the same sample period The start signal always resets the state of the code generator The start signal...

Page 66: ...ers ATSC implements ATSC Advanced Television Systems Committee stan dard 207 187 shortened RS code CCSDS implements CCSDS Consultative Committee for Space Data Systems standard 255 223 full length RS...

Page 67: ...e polynomial for the given symbol width The default polynomials for the specified symbol width are Generator Start specifies the Galois field logarithm of the first root of the generator polynomial g...

Page 68: ...ither the Hamming or Euclidean metric is used to determine the cost The cost determines the distance to each state in the Viterbi trellis The second and final decoding step is to trace backwards throu...

Page 69: ...he output port is of type UFix1_0 Note This version of the Viterbi Decoder is not recommended for implementation of punctured codes Block Parameters Dialog Box Figure 3 45 Viterbi Decoder block parame...

Page 70: ...ble for Soft Coding only Other parameters used by this block are described in the Common Parameters section of the previous chapter The Viterbi Decoder block cannot be placed in an enabled subsystem i...

Page 71: ...s the selected integer rate change factor The transfer function for a single comb stage is H z 1 z RM As seen in the two figures below the CIC filter cascades N integrator sections together with N com...

Page 72: ...e 8 to 16384 inclusive Differential Delay 1 or 2 Other parameters used by this block are described in the Common Parameters section of the previous chapter The CIC block cannot be placed in an enabled...

Page 73: ...ator and the sum is quantized by truncation The quantized value is then used to index into the Sine Cosine Lookup Table mapping phase space into time The phase increment is defined by the following re...

Page 74: ...ion specifies the block output to be sine cosine or both Negative Sine when checked the sine output is negated Negative Cosine when checked the cosine output is negated Output Width number of bits in...

Page 75: ...f 2 The number of bits is determined in one of two ways If the offset type is Register the number of bits is set to the width of the data port If the offset type is Constant the number of bits is infe...

Page 76: ...he FFT block parameters dialog box can be invoked by double clicking the icon in your Simulink model Figure 3 50 FFT block parameters dialog box Parameters specific to the FFT block are Number of Samp...

Page 77: ...vious chapter The FFT block cannot be placed in an enabled subsystem in System Generator v2 1 See the Enabled Subsystems section within the MATLAB I O library documentation explanation for more detail...

Page 78: ...data sizes The Core datasheets can be found on your local disk at For Virtex XILINX coregen ip xilinx primary com xilinx ip vfft doc c_ff t1024_v1_0 pdf XILINX coregen ip xilinx primary com xilinx ip...

Page 79: ...l FIR filters multichannel mode An N tap filter is defined by N filter coefficients or taps h 0 h 1 h n 1 Here each h i is a Xilinx fixed point number The filter block accepts a stream of Xilinx fixed...

Page 80: ...depends on the structure of the sequence of filter taps You can choose one of these inferred from coefficients none symmetric negative symmetric half band and interpolate fir Number of bits per coeff...

Page 81: ...this adds latency it has the benefit of reducing the hardware required for the filter Refer to the core datasheet for more details of the filter modes and parameters The core datasheet can be found o...

Page 82: ...add and subtract This determines whether the block is adder or subtractor based Feedback Scaling specifies the feedback scale factor to be one of the following 1 1 2 1 4 1 8 1 16 1 32 1 64 1 128 or 1...

Page 83: ...Addition Subtraction or Addition Subtraction When Addition Subtraction is selected the block operation is determined by the sub input port which must be driven by a 1 bit unsigned signal When the sub...

Page 84: ...block implements a gain operator with output equal to the product of its input by a constant value This value can be a MATLAB expression that evaluates to a constant Block Parameters Dialog Box The b...

Page 85: ...Information for Core allows specification of placement layout shape that will be used when implementing the core in hardware Placement Style specifies the layout shape in which the multiplier core wil...

Page 86: ...1 and 64 inclusive Otherwise the block is implemented as a synthesizable VHDL module The Core datasheet can be found on your local disk at XILINX coregen ip xilinx eip1 com xilinx ip baseblox_v5_0 do...

Page 87: ...ies that the block must align binary points automatically If not selected all inputs must have the same binary point position Other parameters used by this block are explained in the Common Parameters...

Page 88: ...implemented either as a parallel multiplier that operates on the full width data faster and larger or as a sequential multiplier that computes the result from smaller partial products slower and small...

Page 89: ...simulation only the hardware implementation Use Placement Information for Core allows specification of placement layout shape that will be used when implementing the core in hardware Placement Style s...

Page 90: ...ameters dialog box Parameters used by this block are explained in the Common Parameters section of the previous chapter Xilinx LogiCORE If the Implement with Xilinx Smart IP Core checkbox is selected...

Page 91: ...parameter specific to the Relational block is Comparison Operation specifies the comparison operation computed by the block Other parameters used by this block are explained in the Common Parameters...

Page 92: ...3 Scale block parameters dialog box The only parameter that is specific to the Scale block is Scale Factor It can be a positive or negative integer The output of the block is i2k where i is the input...

Page 93: ...he previous chapter The Shift block does not use a Xilinx LogiCORE SineCosine The Xilinx Sine Cosine block computes sin x and or cos x It stores a reference sinusoid in a read only memory ROM whose de...

Page 94: ...ected the cosine output is negated Output Width specifies the number of bits in the output The valid range is from 4 to 32 inclusive The output is stored as a two s complement value with one integer s...

Page 95: ...ipeline for block ROM implementations is 1 thus the minimum latency is 1 The maximum latency for block ROM is also 1 except for the cases outlined in the table below The Core datasheet can be found on...

Page 96: ...ersa during Simulink simulation Define I O ports for the top level of the HDL design generated by System Generator A Gateway In block defines a top level input port and a Gateway Out block defines a t...

Page 97: ...r The DownCount subsystem is stalled for a single sample period when the CoefCount counter value is equal to the number of filter taps in this case 96 taps Figure 3 67 Example of enabled subsystem The...

Page 98: ...IOBs are put in the user constraint file ucf produced by System Generator This means the paths from the IOBs to synchronous elements are not constrained If Data Rate is selected the IOBs are constrai...

Page 99: ...cations are package specific For the above example if a Virtex E 2000 in a FG680 package is used the location constraints for the Din bus can be specified in the dialog box as A36 C36 B36 D35 This is...

Page 100: ...rovided on the System Generator block and the sample rate of the Gateway relative to the other sample periods in the design For example the following OFFSET OUT constraints are generated for a Gateway...

Page 101: ...ystem Generator v2 1 See the Enabled Subsystems section within the MATLAB I O library documentation explanation for more details Quantization Error Blocks Clear Quantization Error The Clear Quantizati...

Page 102: ...1 the data input ports on Port A and Port B should have an unsigned arithmetic type with binary point at 0 The output ports labeled A and B have the same types as the corresponding input data ports Th...

Page 103: ...e memory has been set to an initial value of 5 and the address bit is specified as 4 When using No Read On Write mode the output is unaffected by the address line and the output is the same as the las...

Page 104: ...lue Vector specifies the initial memory contents The size and precision of the elements of the initial value vector are based on the data format specified for Port A When the vector is longer than the...

Page 105: ...blkmemdp_v3_2 do c dp_block_mem pdf Table Maximum Width for Various Depth Ranges Virtex Virtex E Depth Width 2 to 512 256 513 to 1024 256 1025 to 2048 256 2049 to 4096 192 4097 to 8192 96 8193 to 16K...

Page 106: ...that no more data reside in the memory The FIFO can be implemented either using distributed or block RAM If distributed memory is selected the maximum depth of the FIFO is 256 If block RAM is used the...

Page 107: ...giCORE Synchronous FIFO V3 0 The core datasheet can be found on your local disk at XILINX coregen ip xilinx eip1 com xilinx ip sync_fifo_v3_0 d oc sync_fifo pdf ROM The Xilinx ROM block is a single po...

Page 108: ...Vector specifies the initial value When the vector is longer than the ROM depth the vector s trailing elements are discarded When the ROM is deeper than the vector length the ROM s trailing words are...

Page 109: ...eter is selected LogiCORE Distributed Memory V5 0 is used The depth must be between 16 and 65536 inclusive for Virtex II and Table Maximum Word Width for Various Depth Ranges Virtex Virtex E Depth Wid...

Page 110: ...same arithmetic type width and binary point position The block has two possible implementations using either block or distributed memory Each data word is associated with exactly one address that can...

Page 111: ...ut ports have a value of zero at clock 0 otherwise they have a value of NaN not a number Write Mode specifies the memory behavior to be Read Before Write Read After Write or No Read On Write There are...

Page 112: ...ode the output is unaffected by the address line and the output is the same as the last output when the WE was 0 For the other two modes the output is obtained from the location specified by the addre...

Page 113: ...milies The word width must be between 1 and 1024 inclusive The Core datasheet for the Single Port Block Memory can be found locally at Table Maximum Word Width for Various Depth Ranges Virtex Virtex E...

Page 114: ...st and efficient implementation For example a state machine with 8 states 1 input and 2 outputs that are registered can be realized with a single block RAM that runs at more than 150 MHz in a Xilinx V...

Page 115: ...ram and table The table lists the next state and output that result from the current state and input For instance if the current state is 3 and the input is 1 the next state is 1 and the output is 1 i...

Page 116: ...ialog box The maximum number of states is limited by the depth of the distributed RAM For the Virtex family the maximum number of states supported is 4K and for Virtex II it is 64K Xilinx LogiCORE Thi...

Page 117: ...onsider the problem of designing a state machine to recognize the pattern 1011 within a serial stream of bits The state transition diagram and equivalent transition table are shown below Figure 3 81 M...

Page 118: ...e output of the state machine The next state logic and state register in this block are implemented with high speed dedicated block RAM The output logic is implemented using a distributed RAM configur...

Page 119: ...p c_dist_mem_v5_0 doc dist_mem pdf Registered Mealy State Machine The Xilinx Registered Mealy State Machine block implements a state machine whose output depends on both the current state and input Th...

Page 120: ...tion table are shown below Figure 3 85 Registered Mealy State Machine example transition diagram and table The table lists the next state and output that result from the current state and input For in...

Page 121: ...columns correspond to the input value Block Parameters Dialog Box The block parameters dialog box can be invoked by double clicking the icon in your Simulink model Figure 3 87 Registered Mealy State M...

Page 122: ...lock RAM width and depth limitations are described in the online help for the Single Port RAM block Xilinx LogiCORE This block uses Version 3 2 of the Xilinx Single Port Block Memory LogiCORE The Core...

Page 123: ...chine block except that its output logic is registered A block diagram of this type of state machine is shown below Figure 3 88 Registered Moore State Machine block diagram The block is configured by...

Page 124: ...table are shown below Figure 3 89 Registered Moore State Machine example transition diagram and table The table lists the next state and output that result from the current state and input For exampl...

Page 125: ...not affect the output of the state machine Block Parameters Dialog Box The block parameters dialog can be invoked by double clicking the icon in your Simulink model Figure 3 91 Registered Moore State...

Page 126: ...AM sizes necessary for various state machines Xilinx LogiCORE This block uses Version 3 2 of the Xilinx Single Port Block Memory LogiCORE The block RAM width and depth limitations are described in the...

Page 127: ...ectory where you extracted setup dll Type setup at the MATLAB console prompt This will launch the System Generator installer Uninstalling previous System Generator directories If you have previously i...

Page 128: ...that cannot be realized with Xilinx blocks For example the design might require a FIR filter whose capabilities differ from those in the filter supplied in the Xilinx Blockset Black boxes provide a w...

Page 129: ...level model you can see the bits reverse in the output scope This simulation is running the MATLAB function bit_reverse Figure 4 1 Output of example black box function Black Box window The Xilinx Bla...

Page 130: ...st have a mixed language simulator and a mixed language synthesis compiler Tools that support mixed language projects usually have special restrictions and instructions for their mixed language interf...

Page 131: ...ge designs To synthesize using Synplify open the project file for example my_project_synplicity prj in Synplify Tell the tool to add your black box files to the project The procedure for a Leonardo Sp...

Page 132: ...e same results since this block is implemented using a SRL16 and cannot be packed into an IOB Use the IOB Timing Constraint option Data Rate Set FAST Attribute on all Gateway In and Gateway Out blocks...

Page 133: ...en obtained and can do so using considerably less time Constraints supply the following information The period to be used for the system clock The speed with respect to the system clock at which vario...

Page 134: ...ampler divides the sample rate by three In this design the system clock period is 10 ns specified in the parameters dialog box for the System Generator block so the clock periods are 10 ns for the FIR...

Page 135: ...ce1_group TS_clk 1 TIMESPEC TS_ce2_group_to_ce3_group FROM ce2_group TO ce3_group TS_clk 2 TIMESPEC TS_ce3_group_to_ce1_group FROM ce3_group TO ce1_group TS_clk 1 TIMESPEC TS_ce3_group_to_ce2_group FR...

Page 136: ...constraint entry in the UCF file that accompanies this design has failed while a case insensitive search is in progress The result of the case insensitive search will be used but warnings will accomp...

Page 137: ...nx ISE 4 1i Project Navigator using the XST synthesis compiler and ModelSim simulator my_project_testbench vhd the top level VHDL testbench file associated with the top level VHDL source file in the p...

Page 138: ...138 Xilinx Development System Xilinx System Generator v2 1 Reference Guide sysgen log log file xlRunScripts log log file showing status of post processing scripts run by System Generator...

Page 139: ...ilinx 4 1i software tools environment This file is called name of project npl We will use the name my_project npl for the following discussion Opening a System Generator project You may double click o...

Page 140: ...Properties dialog From this window you can change your part package speed and synthesis compiler Figure 5 2 Customizing Project Navigator properties Implementing your design You have many options with...

Page 141: ...ream for your design Now that you have generated a bitstream for your design you have access to all the files that were produced on the way to bitstream creation For example if you wish to see how you...

Page 142: ...sociated with testbench in Project Navigator The System Generator has already associated the four ModelSim do files with each of the four types of simulation To see what do files will run when each ty...

Page 143: ...roperties dialog will open Select EDIF as the design flow type Figure 5 8 EDIF design flow in Project Navigator Now you may add your EDIF files to the project as sources From the Project Navigator pul...

Page 144: ...linx vhdl xilinxcorelib This is the location where MXE expects to find your Xilinx compiled libraries so you do not need to make any changes to your modelsim ini file This file should point to the cor...

Page 145: ...automatically use this ModelSim simulator Figure 5 10 Processes associated with System Generator testbench in Project Navigator Xilinx software tools resources Documentation tutorials and other Xilin...

Page 146: ...how the capabilities of the System Generator software and the Xilinx blocks These demonstration designs may be accessed by selecting the Demos menu choice from the MATLAB Help menu Figure 6 1 Opening...

Page 147: ...rates a project file prj file for use with the synthesis compiler Synplify from Synplicity leon pl generates a project file tcl file for use with the synthesis compiler Leonardo Spectrum from Exemplar...

Page 148: ...148 Xilinx Development System Xilinx System Generator v2 1 Reference Guide...

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