Xilinx Spartan-3A DSP FPGA Series, Technical Reference Manual

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Hardware overview
13
Table 1 FPGA USB/System ACE interface pinout
FPGA pin Description FPGA pin Description
AE13 sysace_clk_in (System ACE only) AD21 sace_usb_a_1
AE23 sace_mpce (System ACE only) AA17 sace_usb_a_2
AA18 sysace_mpirq (System ACE only) AE21 sace_usb_a_3
W17 usb_csn (USB only) V16 sace_usb_a_4
AD22 usb_hpi_int (USB only) AC20 sace_usb_a_5
AC21 sace_usb_oen AD20 sace_usb_a_6
V17 sace_usb_wen U16 sace_usb_a_7
AF4 sace_usb_a_0 AF20 sace_usb_a_8
W9 sace_usb_a_1 AE20 sace_usb_a_9
Y9 sace_usb_a_2 AC19 sace_usb_a_10
AE3 sace_usb_a_3 AF19 sace_usb_a_11
AF3 sace_usb_a_4 AE19 sace_usb_a_12
V15 sace_usb_a_5 AD19 sace_usb_a_13
U15 sace_usb_a_6 AC16 sace_usb_a_14
Y17 sace_usb_a_0 AB16 sace_usb_a_15
2. USB peripheral port
Type B connector. Used to connect peripheral USB devices to the XtremeDSP Spartan-3A DSP Development
Board.
3. USB host port
Type A connector. Used to connect a host device to the XtremeDSP Spartan-3A DSP Development Board.
4. AC’97 SoundaMAX codec
Analog Devices AD1981B. The device supports 16-bit stereo audio and sampling rates up to 48 kHz. The
sampling rate for recording and playback may also be different.
Note
The codec’s reset is shared with the reset signal of the flash memory devices. It is designed to be asserted
when the development board is turned on or reset.
5. DVI connector
The DVI connector is used to connect an external video monitor (DVI or VGA) to the XtremeDSP Spartan-
3A DSP Development Board.
Note
The VGA monitor can be connected to the development board with a DVI-to-VGA adaptor (sold separately).
6. Display controller device
The DVI circuitry uses a Chrontel CH7301C capable of 24-bit color and 1600 × 1200-pixel resolution. The
display controller device drives the digital and analog signals to the DVI connector (
5 ). The display controller
device is controlled through the I
2
C bus.
The DVI connector supports the I
2
C protocol, allowing the development board to read a monitor’s
configuration parameters. The parameters can then be read by the FPGA through the I
2
C bus. See
I
2
C bus
addressing
for details.