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SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
Chapter 1:
SP605 Evaluation Board
14. IIC Bus
The SP605 implements three IIC bus interfaces at the FPGA.
The MAIN IIC bus hosts four items:
•
FPGA U1 Bank 1 “MAIN” IIC interface
•
8-Kb NV Memory U4
•
FMC LPC connector J2
•
2-Pin External Access Header J45
The DVI IIC bus hosts two items:
•
FPGA U1 Bank 2 DVI IIC interface
•
DVI Codec U31 and DVI connector P3
The SFP IIC bus hosts two items:
•
FPGA U1 Bank 0 SFP IIC interface
•
SFP module connector P2
The SP605 IIC bus topology is shown in
.
X-Ref Target - Figure 1-11
Figure 1-11:
IIC Bus Topology
U1
P3
U31
BANK 1
IIC_
S
DA_MAIN
IIC_
S
CL_MAIN
IIC_
S
DA_
S
FP
IIC_
S
CL_
S
FP
IIC_
S
DA_DVI
IIC_
S
CL_DVI
U4
J2
IIC_CLK_DVI_F
S
T MICRO
M24C08-WDW6TP
FMC LPC
Col
u
mn C
2 K
b
EEPROM on
a
ny FMC LPC
Mezz
a
nine C
a
rd
P2
S
FP Mod
u
le
Connector
IIC_
S
DA_DVI_F
BANK 0
BANK 2
FPGA IIC
INTERF
A
C
E
Addr:
0b1010000
Addr:
0b1110110
Addr:
0b1010100
thro
u
gh
0b1010111
Addr:
0b1010010
Addr:
0b1010000
J45
2-Pin Extern
a
l
Acce
ss
He
a
der
DVI Connector
DVI CODEC
CHRONTEL
CH730C-TF
LEVEL
S
HIFTER
UG526_11_092609