Xilinx MP3 NG Application Note Download Page 27

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MP3 NG: A Next Generation Consumer Platform

XAPP169 (v1.0) November 24, 1999

www.xilinx.com

1-800-255-7778

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© 1999 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaim-
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11/24/99

1.0

Initial release.

Summary of Contents for MP3 NG

Page 1: ...short term Like any new market the feature set of MP3 players is likely to change as more users buy them Key dynamics in this market include Copy Protection While the Secure Digital Music Initiative S...

Page 2: ...t that loud sounds mask out the listener s ability to perceive quieter sounds in the same frequency range The encoder uses this property to remove information from the signal that would not be heard a...

Page 3: ...sheet for the RC32364 can be found at the following URL http www idt com docs 79RC32364_DS_32100 pdf The RC32364 s MMU consists of address translation logic and a Translation Lookaside Buffer TLB cap...

Page 4: ...AG ICE Interface TLB MMU lockable write back write through Generation Unit RC32364 Bus Interface Unit 8kB I Cache lockable 2 set RISCore32300 Internal Bus Interface RISCore4000 Compatible w RISCore323...

Page 5: ...it multiplexed address data bus The bus offers a rich set of signals to control transfers of which only a subset was required for this application Figure 4 shows the timing for read transactions on th...

Page 6: ...l port is an industry standard I2 C slave interface I2 C is a multidrop 2 wire serial interface consisting of a clock SCL and data SDA and operating at up to 100 kHz See Figure 7 Control Port Timing T...

Page 7: ...4343 documentation as Serial Audio Format 2 Figure 7 gives an overview of serial port timing when in this mode t buf t hdst t hdst t low t r t f t hdd t high tsud tsust tsusp Stop Start Start Stop Rep...

Page 8: ...s a parameter called NVB that is the number valid blocks that the device contains The value of NVB varies from device to device and is specified to have a minimum of 1014 a maximum of 1024 and typical...

Page 9: ...L synchronous interface Figure 10 shows the block diagram for this device Figure 11 shows the MT48LC1M16A1 read timing of the device The complete data sheet for the MT48LC1M16 can be found at the foll...

Page 10: ...MH 256 2 048 BANK0 MEMORY ARRAY 2 048 x 256 x 16 ROW DECODER ROW ADDRESS LATCH 11 12 ADDRESS REGISTER 12 SENSE AMPLIFIERS I O GATING DQM MASK LOGIC DATA INPUT REGISTER DATA OUTPUT REGISTER 16 16 Figur...

Page 11: ...s a simple 8 bit microprocessor bus that can be configured to operate in a multiplexed or non multiplexed mode The multiplexed mode is more attractive from a software perspective since it supports ran...

Page 12: ...is shown in Figure 14 The software components fall into four categories RTOS A Real Time Operating System is included in the software architecture in order to simplify the management of resources and...

Page 13: ...I manager would also spawn separate processes for value added features such as an appointment calendar or a phone book as needed MP3 Decoder and Audio ISR The MP3 decoder runs as an independent proces...

Page 14: ...s detected in a valid block this code is also responsible for copying the data to an unused block and marking the block in which the error was detected as bad Code Initialization This function copies...

Page 15: ...uests from the CPU Interface and the LCD Controller are handled by using a simple rotating priority scheme The arbiter block also controls the multiplexers that select which set of transfer control si...

Page 16: ...the IRDA and audio DAC interrupts out onto the CPU interrupt signals The bus state machine converts the signaling on the CPU bus into the format used on the local IP bus or if the transaction is to th...

Page 17: ...Description CPU_MASTERCLK Output All bus timing is relative to this clock The CPU core frequency is derived by multiplying this clock CPU_AD 31 0 I O High order multiplexed address and data bits CPU_...

Page 18: ...between different factors Longer bursts are more efficient since the SDRAM access overhead is amortized over a larger number of data words Smaller bursts reduce the size of the FIFO and also reduce b...

Page 19: ...ements the data path required to map the 8 and 16 bit memory devices to the 32 bit IP bus While the RC32364 is capable of fetching instruc tions and data from devices with varying bus widths having th...

Page 20: ...and the nine I O pads listed in Table 3 There is no software support required for this block FLASH Controller The largest cost associated with this design is the large amount of FLASH memory 32 MB or...

Page 21: ...bytes using a Hamming code the following relationship must be satisfied Since there are 32 512 16 cache lines per page a total of 36 bytes are needed for ECC storage Recall that 16 bytes are available...

Page 22: ...terrupt every 557 ms See Figure 21 Table 4 FLASH Controller Interface Signal Summary Signal Type Description FL_CE_N 3 0 Output Device chip enables active Low FL_ALE Output Address latch enable FL_WE_...

Page 23: ...s infrequent use When the system is in operation the serial audio port is in use most of the time Therefore dedicated hardware is provided for implementing the transfer protocol and for delivering an...

Page 24: ...r This lets the system software read the X and Y coordinate resistance values that result from the user touching the screen The system software handles linearization and filters out transient touch ev...

Page 25: ...s density 3 3V operation 176 user I O and is packaged in a space saving FG256 BGA package Conclusion The design that has been outlined meets both original design objectives Even with budgetary pricing...

Page 26: ...ogies KM29U64000T 8M x 8 bit NAND Flash Memory April 1999 Samsung Semiconductor Table 9 NG Player Semiconductor BOM Item Qty Mfg Part Number Description Volume Unit Cost Ext Cost 1 4 Samsung KM29U6400...

Page 27: ...evision History 1999 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaim ers are as listed at http www xilinx com legal htm All other trademarks and registe...

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