Modifying Xilinx ML605 for Direct JTAG Access
8
©1989-2021 Lauterbach GmbH
Photo of the “JTAG to Xilinx ML605” adaptor. The red circle marks the extra pin for the last device TDO.
Miscellaneous Information
This section gives some additional information on miscellaneous topics.
•
The schematics of the EVB Xilinx ML605 are available from
http://www.xilinx.com/support/documentation/boards_and_kits/xtp052_ml605_schematics.pdf
•
The jumper J24 on ML605 cannot be used for JTAG debugging because its JTAG lines are not
connected to the SysACE and FPGA. According to a comment in the board schematics it is only
intended for reprogramming a CPLD during production testing.
