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Introduction

XAPP979 (v1.0) February 26, 2007

www.xilinx.com

 2

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Introduction

This application note accompanies a reference system built on the ML403 development board.

Figure 1

 is a block diagram of the reference system.

The system uses the embedded PowerPC (PPC) as the microprocessor and the OPB IIC core.

IIC Primer

Figure 2

 shows components on an IIC bus.Two IIC masters and three IIC slaves are shown.

The master is responsible for setting up transactions. This includes generating the clock on
SCL and defining which slave is involved in the communication, with an address field, and
which component is transmitting and which component is receiving. Some components are
slave only, while others can transition between master and slave operation.

Figure 3

shows the START and STOP conditions. A START condition is a falling edge on SDA

when SCL is high. A STOP condition is a rising edge on SDA when SCL is high. During data
transfer, the data line is stable on SDA when SCL is high. Data transitions on SDA when SCL
is low. Note that the START and STOP conditions are special conditions, violating the rule that
data cannot transition while SCL is high.

Figure 1: OPB IIC Reference System Block Diagram

Figure 2: IIC Bus

Figure 3: Start and Stop Conditions

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Summary of Contents for ML403

Page 1: ...403 Embedded Development Platform The reference system is Base System Builder BSB based An IIC primer is given and an OPB IIC register reference is provided The Xilinx Microprocessor Debugger XMD commands are used for verifying that the OPB IIC core operates correctly Several software projects illustrate how to configure the OPB IIC core set up interrupts and do read and write operations Some of t...

Page 2: ...nsmitting and which component is receiving Some components are slave only while others can transition between master and slave operation Figure 3 shows the START and STOP conditions A START condition is a falling edge on SDA when SCL is high A STOP condition is a rising edge on SDA when SCL is high During data transfer the data line is stable on SDA when SCL is high Data transitions on SDA when SC...

Page 3: ...one Not Acknowledge on the IIC bus The distinction between a Not Acknowledge and a No Acknowledge is that Not Acknowledge occurs after a master has read a byte from a slave and a No Acknowledge occurs after a master has written a byte to a slave A synchronized SCL is generated with its LOW period determined by the device with the longest low period and its HIGH period determined by the device with...

Page 4: ... If a master is not driving the IIC bus low and the bus is low the master knows that another master is driving the IIC bus If a master cannot get the SDA or SCL to go high it loses arbitration When a master loses arbitration it stops transmission The master driving the bus with the last low when the other master s drives high becomes the master of the bus Reference System Specifics In addition to ...

Page 5: ...trol Register C_BASEADDR 0x100 Status Register C_BASEADDR 0x104 Transmit FIFO C_BASEADDR 0x108 Receive FIFO C_BASEADDR 0x10C Slave Address Register C_BASEADDR 0x110 Transmit FIFO Occupancy C_BASEADDR 0x114 Receive FIFO Occupancy C_BASEADDR 0x118 Ten Bit Slave Address Register C_BASEADDR 0x11C Receive FIFO Programmable Depth Interrupt Register C_BASEADDR 0x120 General Purpose Output C_BASEADDR 0x12...

Page 6: ...are because arbitration for the bus has been lost a STOP condition is not generated 30 Tx FIFO Reset Transmit FIFO Reset This bit must be set if arbitration is lost or if a transmit error occurs to flush the FIFO 31 EN OPB IIC Enable This bit must be set before any other CR bits have any effect Table 4 Status Register Bit Definitions Bit s Name Description 0 23 N A Reserved 24 Tx_FIFO_ Empty Trans...

Page 7: ... or general call if enabled This bit is cleared when a stop condition is detected or a repeated start occurs 31 ABGC Addressed By a General Call This bit is set high when another master has issued a general call and the general call enable bit is set high CR 1 1 Table 5 Interrupt Status Register Bit Name Description 24 TFHE Transmit FIFO Half Empty 25 NAAS Not Addressed as Slave 26 AAS Addressed a...

Page 8: ...f on the board to disable its hardware write protect The IIC bus is extended to the expansion connector to allow additional devices to be added to the IIC bus Figure 9 shows IIC Bus Devices on the ML403 Figure 9 ML403 IIC Bus The 24LC04 is organized as two blocks of 256 bytes It has a page write buffer of up to 16 bytes The 24LC04 operates as an IIC slave The 24LC04 accepts a control byte which co...

Page 9: ...and sequential read operations ML403 Board Information According to the MicroChip 24L024B data sheet the ML403 board has a low level output current IOL of 3 0 mA at a VCC of 2 5v The ML403 boards are shipped in the configuration shown in Figure 11 The board must be modified for this design to work correctly Replace the 10K Ohm R70 and R71resistors with 833 or 1K Ohm resistors See Answer Record 240...

Page 10: ...ML403 Board Information XAPP979 v1 0 February 26 2007 www xilinx com 10 R The resistors are located on the board as shown in Figure 12 Figure 12 ML40x Resistors X979_12_022307 ...

Page 11: ...dent on the voltage Figure 13 Expansion Header NC FPGA_PROM_CPLD_TMS FPGA_PROM_CPLD_TCK EXPANSION_TDO CPLD_TDO GPIO_LED_N GPIO_SW_N GPIO_LED_C GPIO_SW_C GPIO_LED_W GPIO_SW_W GPIO_LED_S GPIO_SW_S GPIO_LED_E GPIO_SW_E GPIO_LED_0 GPIO_LED_1 GPIO_LED_2 GPIO_LED_3 NC NC 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IIC_SCL VCC2V5 Level Translation MOSFETs Extern...

Page 12: ...Configure Aardvark Adapter window is organized into two major sections list of available adapters connected to the computer and list of the six operational modes The main application window is divided into two sections The top section contains the modules used with the Aardvark Adapter The bottom section contains the transaction log which tracks all transactions that the Aardvark sends or receives...

Page 13: ...er Executing the Reference System using the Pre Built Bitstream and the Compiled Software Applications To execute the system using files inside the ml403_ppc_opb_IIC ready_for_download directory follow these steps 1 Change to the ml403_ppc_opb_IIC ready_for_download directory 2 Use iMPACT to download the bitstream by using the following impact batch xapp cmd Figure 15 Aardvark Control Center Figur...

Page 14: ...Receive Occupancy registers all registers are writeable mwr 0x42600100 0xFFFFFFFF mrd 0x42600100 1 Using XMD commands verify that the OPB IIC registers can be written and read as defined in Tables 2 5 Software Projects The reference system contains the following software projects In each software project directory there is a src sub directory for the source code The connections in Figure 9 are use...

Page 15: ... FREE BUS command When the bus is free the OPB IIC master initiates a bus transaction repeated_start This project transmits and receives the data using the high level L1 driver The IIC devices on the ML300 ML310 ML410 boards do not support the repeated start option The ML403 OPB IIC is configured as a master and the Aardvark Adapter IIC is configured as a IIC slave The OPB IIC writes the data to t...

Page 16: ...ss is 0x70 Click Master Write to generate the transaction Running the Applications In XPS select the Applications tab under the Project Information Area to view the Software Project Figure 19 shows the structure of the dynamic_eeprom project Make the dynamic_eeprom project active and the remaining software projects inactive Figure 18 Slave Example X979 18 012907 Figure 19 Selecting the eeprom Soft...

Page 17: ... ML403 board Start up a HyperTerminal Set Bits per second to 9600 Data bits to 8 Parity to None and Flow Control to None as shown in Figure 20 From XPS start XMD and enter rst Invoke GDB and select Run to start the application as shown in Figure 21 The eeprom c code written for the ML403 shown in the figure runs without any modifications on this reference system Figure 20 HyperTerminal Parameters ...

Page 18: ...he opb_iic core The following steps are used to insert a core and analyze OPB IIC problems with ChipScope 1 Invoke XPS Run Hardware Generate Netlist 2 In the iic cdc file change the path design_directory name to the directory in which the design files are installed Three paths need to be changed 3 Run Start Programs ChipScope Pro ChipScope Inserter 4 From ChipScope Inserter run File Open Project i...

Page 19: ...XPS run Hardware Generate Bitstream and Device Configuration Download Bitstream Do not rerun Hardware Generate Netlist as this overwrites the implementation iic_eeprom_wrapper ngc produced by the step above Verify that the file size of the opb_iic_wrapper ngc with the inserted core is significantly larger than the original version 9 Invoke ChipScope Pro Core Analyzer by selecting Start Programs Ch...

Page 20: ...ults 11 Set the trigger in the Trigger Setup window The trigger used depends on the problem being debugged Change the Windows to N samples to a setting of 100 Arm the trigger by selecting Trigger Setup Arm or clicking on the Arm icon As shown in Figure 24 the trigger setup is to trigger when gen_start is High 12 Run XMD and or GDB to activate the trigger patterns which cause ChipScope to display m...

Page 21: ...ned in the Cadence Design System Inc Simvision design tool by selecting File Open Database Linux Kernel New users of MontaVista Linux should read XAPP 765 Getting Started with EDK and Monta Vista Linux The steps to build and boot a Linux kernel are given below Steps 1 3 7 8 are run on a Linux machine with MontaVista Professional Edition installed 1 Add opt montavista pro host bin and opt montavist...

Page 22: ...February 26 2007 www xilinx com 22 R 5 Under OS and Libraries set the entries as shown in Figure 26 Verify that the target directory is the same as the directory containing the Linux source Figure 26 BSP Settings X979_26_012907 ...

Page 23: ...g An alternative is to enter make menuconfig and generate a new config using the following options Select General Setup Enable IIC Disable PS 2 keyboard Change to dev ram for booting from ramdisk Select Input Core Support Disable all Select Character Devices Disable Virtual Leave Serial enabled Disable Xilinx GPIO and Touchscreen 10 Run make clean dep zImage initrd Verify that the zImage initrd el...

Page 24: ...ppc_opb_iic simulation directory contains waveform log file opb_iic wlf for IIC transactions discussed in this section The opb_iic wlf files are easily loaded into the Modeltech simulator using the File Open command specifying the wlf file type The OPB IIC core has two Finite State Machine FSM The clock FSM has IDLE START SCL_LOW_EDGE SCL_LOW SCL_HIGH_EDGE SCL_HIGH STOP_WAIT states The main FSM ha...

Page 25: ...gister empty Msms Master Slave select Dtr 7 0 Data Transmit Register Adr 7 0 IIC Slave Address Register Ten_adr 7 5 10 bit Slave Address Register Bb Bus Busy Aas Addressed as slave Al Arbitration lost Srw Slave read write Abgc Addressed by general call Data_iic 7 0 IIC data for microprocessor New_rcv_data New data received on IIC bus Tx_under_prev Transmit FIFO Empty IRQs slave_sda SDA value when ...

Page 26: ...P979 v1 0 February 26 2007 www xilinx com 26 R The simulation runs for 2000 ns as shown in Figure 29 There are 3 sections in the simulation shown in the following figures Figure 29 Complete Simulation X979_29_022307 ...

Page 27: ...re 30 the OPB IIC registers are read to verify the correct reset values The interrupt registers are written and read This occurs from 0 10 s Following this an arbitration test is run IIC_AA is initially the bus master with the write CR_AA 0x0d Figure 30 Arbitrartion Lost Test Simulation X979_30_022307 ...

Page 28: ...bitration Lost Test Code write ADR_20 0x20 write CR_20 40 write CR_AA 0x01 write ADR_AA AA write IER_AA 0x04 write RC_FIFO_PIRQ_20 0x0 write DTR_AA 0x0 write CR_AA 0x0D Enables AA as master 5 9us write IPIER_20 0x01 write DTR_20 AA write CR_20 0x0D Enables 20 as master wait_for_intr 30 read IPISR 0xD3 Arbitration lost 260 us write CR_20 0x01 Clears interrupt X979_31_012907 ...

Page 29: ... www xilinx com 29 R The second test shown in Figure 32 runs from 575 s to 790 s Ths master AA receives 3C and 55 from 20 The following stimuli results is seen in the opb_iic wlf file Figure 32 Simulation with iic_AA as Master X979_32_022307 ...

Page 30: ...te DTR_20 0x3C write DTR_20 0x55 write DTR_AA 0x0 General Call write CR_AA 0x0D RSTA TxAK TX MSMS Enable wait_for_intr read SR_AA 0xC4 TFE RFE BB read ISR_AA 0xD4 TFHE DTRE write CR_AA 0x35 RSTA MS EN 547 us write DTR_AA 0x21 write DTR_AA 0xFF write IER_AA 0x08 wait_for_intr waiting for DRR_AA full read SR_AA 0x0C SRW BB 678 us write CR_AA 0x37 Clear FIFO write CR_AA 0x35 read DRR_AA 0x3C write IS...

Page 31: ...bruary 26 2007 www xilinx com 31 R Figure 34 shows the third test shown in opb_iic wlf run from 800 2000 us IIC_20 is the master writing to IIC_AA which is a 10 bit slave Figure 34 Simulation with iic_AA as Master X979_34_012907 ...

Page 32: ...ntr DRR full 0x22 received throttle for 1500 ns write DTR_20 0xF2 Most significant address write DTR_20 0xD5 Least significant address write DTR_20 E1 read TX_FIFO_OCY 0x02read SR_AA 0x8E read DRR_AA 0xAA read SR_AA 0xCE write DTR_20 0xD2 write DTR_20 0xC3 write DTR_20 0xB4 read TX_FIFO_OCY_20 0x05 read SR_20 0x0C SRW BB write DTR_20 0xA5 write DTR_20 0x96 write DTR_20 0x87 write DTR_20 0x78 write...

Page 33: ... EDK and MontaVista Linux ML40x Embedded Development Platform User Guide UG080 v2 5 May 24 2006 ChipScope ILA Tools Tutorial The IIC Bus Specification Version 2 1 January 2000 Philips Semiconductors Revision History The following table shows the revision history for this document Date Version Revision 2 26 07 1 0 Initial Xilinx release ...

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