background image

R

UG133 v1.3.1  January 7, 2005

www.xilinx.com

MicroBlaze Microcontroller Ref Des User Guide

"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. 

CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are 
registered trademarks of Xilinx, Inc. 

The shadow X shown above is a trademark of Xilinx, Inc.

ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, 
CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and 
Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, 
MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, Se, 
Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, 
VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT-
Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry,  XAM, XAPP, X-BLOX +, XC designated products, XChecker, 
XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc. 

The Programmable Logic Company is a service mark of Xilinx, Inc. 

All other trademarks are the property of their respective owners.

Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey 
any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any 
time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for 
the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or 
information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, 
application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are 
responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with 
respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation 
is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices 
and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown 
or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to 
correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability 
for the accuracy or correctness of any engineering or software support or assistance provided to a user.

Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without 
the written consent of the appropriate Xilinx officer is prohibited.

The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2003 Xilinx, Inc. All Rights Reserved. Except as stated 
herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form 
or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent 
of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and 
publicity, and communications regulations and statutes.

Summary of Contents for MicroBlaze

Page 1: ...R MicroBlaze Microcontroller Reference Design User Guide v1 3 1 UG133 v1 3 1 January 7 2005...

Page 2: ...cribed herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one p...

Page 3: ...The following table shows the revision history for this document Version Revision 7 22 04 1 0 Initial Xilinx release 8 27 04 1 1 Edited content imported new images 11 19 04 1 2 Reconfigured book adde...

Page 4: ...the Design and Launching XPS 4 Updating and Generation Hardware Files 5 Downloading Design Files to the FPGA 6 Selecting a Software Application to Run When the FPGA is Configured 6 Loading the Calcul...

Page 5: ...ontroller configurations from which an engineer can choose The soft microcontroller features and peripherals in the FPGA may be used without modification or may be modified and customized using the Xi...

Page 6: ...ce specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http support xilinx com xlnx xweb xil_publications_index jsp Problem...

Page 7: ...connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option_name design_name Braces A list of items from which you must cho...

Page 8: ...peripherals This guide is provided as an aid in getting started and learning how to use the Xilinx Embedded Development Kit EDK tools It does this through examples which show how multiple software im...

Page 9: ...esign includes an Internal Block RAM memory an RS232 UART 4 GPIO blocks and a JTAG_UART used for software debugging This configuration utilizes approximately 50 of a Spartan 3 XC3S200 device Applicati...

Page 10: ...onfigured as output ports to drive the 7 segment LEDs on the board 8 bit GPIO configured as input ports to read onboard dip switches 3 bit GPIO configured as input ports to read push buttons JTAG_UART...

Page 11: ...st application Launching Xilinx Platform Studios XPS Downloading the Reference Designs Go to the MicroBlaze lounge at http www xilinx com microblaze_mcu_refdes1 Download the reference design starting...

Page 12: ...pplication can run any number of Software Applications When the Base System Wizard is used to create a Hardware System it also will create a simple Software Application to test the selected Hardware f...

Page 13: ...tstream This will configure the MicroBlaze Microcontroller program and Data memory with the software application already pre loaded This means that as soon as the FPGA has been successfully configured...

Page 14: ...f the PC On the PC using hyperterminal make certain that the bit rate is set for 57600 bps on the serial port 3 Turn on the power on to the Spartan 3 Evaluation Board 4 In XPS to make sure that the EL...

Page 15: ...w1 ON Sw0 ON Where Word 1 is 1 and Word 0 is 3 Add 3 1 4 Sub 3 1 2 Mult 3 1 3 Each time one of the Push Button switches is pressed the result should be displayed in decimal on the 7 Seg display and it...

Page 16: ...over it Verify that this is the case for microblaze_0_bootloop Project TestApp and Project Calculator_App If any are set please Right click and confirm that Mark to Initialize BRAMs is not checked If...

Page 17: ...select Tools Software Debugger to open the GDB interface Source Window 2 Choose TestApp from the User Application window 3 In GDB select the File Target Settings to display the Target Selection dialog...

Page 18: ...ram repeat the procedure in section Loading the TestApp Software Application with XMD_STUB Start with step 1 and choose Calculator_App in step 5 instead of TestApp See Running the Calculator_App progr...

Reviews: