Xilinx LogiCORE MicroBlaze, Product Manual

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MicroBlaze Micro Controller System v1.3 www.xilinx.com 28
PG048 December 18, 2012
Chapter 4: Customizing and Generating the Core
Parameter - Port Dependencies
The width of many of the MicroBlaze MCS signals depends on design parameters. The
dependencies between the design parameters and I/O signals are shown in Table 4-9 .
Table 4-7: Internal LMB BRAM IF Controller Parameters Settings (DLMB Controller)
Parameter Name Feature/Description Value
C_BASEADDR LMB BRAM base address 0
C_HIGHADDR LMB BRAM high address Value of MicroBlaze
MCS
Parameter C_MEMSIZE
C_MASK LMB decode mask 0x80000000
C_LMB_AWIDTH LMB address bus width 32
C_LMB_DWIDTH LMB data bus width 32
C_ECC Implement error correction and detection
All other ECC as well as AXI and PLB parameters are don’t
care
0 = No ECC
Table 4-8: MicroBlaze Debug Module Parameters Settings
Parameter Name Feature/Description Value
C_FAMILY FPGA architecture Value of MicroBlaze
MCS
Parameter C_FAMILY
C_MB_DBG_PORTS Number of MicroBlaze debug ports 1
C_USE_UART Enables the UART interface.
All other UART as well as AXI and PLB parameters are
don’t care
0
Table 4-9: Parameter-Port Dependencies
Parameter Name Ports (Port width depends on parameter)
C_INTC_INTR_SIZE INTC_Interrupt
C_GPO1_SIZE GPO1
C_GPO2_SIZE GPO2
C_GPO3_SIZE GPO3
C_GPO4_SIZE GPO4
C_GPI1_SIZE GPI1
C_GPI2_SIZE GPI2
C_GPI3_SIZE GPI3
C_GPI4_SIZE GPI4