Xilinx LogiCORE IP, Product Manual

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XAUI v12.3 Product Guide www.xilinx.com 12
PG053 April 6, 2016
Chapter 2
Product Specification
Standards Compliance
The XAUI IP core is designed to the standard specified in clauses 47 and 48 of the
10-Gigabit Ethernet specification IEEE Std. 802.3-2012 .
Performance
This section contains the following subsections:
• Latency
• Speed Grades
Latency
These measurements are for the core only; they do not include the latency through the
transceiver. The latency through the transceiver can be obtained from the relevant
transceiver user guide.
Transmit Path Latency
As measured from the input port
xgmii_txd[63:0]
of the transmitter side XGMII (until
that data appears on the
txdata
pins on the internal transceiver interface on the
transceiver interface), the latency through the core for the internal XGMII interface
configuration in the transmit direction is four
clk
periods of the core input
usrclk
.
Receive Path Latency
Measured from the input into the core encrypted hdl logic from the
rxdata
pins of the
internal transceiver interface until the data appears on
xgmii_rxdata[63:0]
of the
receiver side XGMII interface, the latency through the core in the receive direction is equal
to 4
–
5 clock cycles of
usrclk
.
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