Video In to AXI4-Stream
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PG043 April 24, 2012
Module Descriptions
account in the design of the bridges by providing a small “cushion” or minimum fill level in
the FIFOs so that the pointer pessimism does not cause artifacts.
Underflow Prevention
In addition to the steps for synchronizing flags, extra care must be taken in handling the
empty condition. It is not enough to signal an empty condition, because “reads” of the FIFO
will not stop on empty. Additional read operations must be performed to get the EOL to the
output of the FIFO. This happens routinely at the end of every line, and the FIFO must not
lose any data. That is, underflow is not allowed. When new data is eventually written to the
FIFO, the read must pick up with the first new valid pixel. To do this, the read pointer is
inhibited when the FIFO is empty.
The empty flag asserts coincident with the last available location being clocked into the
output register. The read pointer, however is not advanced to match the write pointer but
remains pointing at the last valid pixel that was read. Subsequent reads, when empty is
asserted, will cause the read_error flag to be asserted, flagging the pixel from the FIFO as
invalid. The data output, however will not change.
Thus, when a read occurs to an empty FIFO, the invalid flag (read_error) is set, and the read
pointer does not increment. In this way, the EOL can be advanced through the pipe by a
series of reads on the empty FIFO. With each read, an invalid pixel backfills the advancing
EOL but the downstream logic can distinguish these from valid pixels.
Pointer Format
It is important to provide an accurate level, and to distinguish between full and empty
conditions when the read and write pointers are equal. This is done by having extra
“revolution” bits on the pointers in addition to the address bits as shown in
At the cost of a couple of extra bits in the pointers, this allows the level calculations and
flags to be unambiguously determined in full and empty conditions.
Read Logic
The function of the read logic is to control the handshaking for the AXI4-Stream bus and to
provide pixels to this bus as rapidly as possible. In general, the strategy for AXI4-Stream is
downstream-greedy. That is, downstream modules take pixels as soon as they are available
and there is buffer space to accommodate them. Since the Video In to AXI4-Stream core is,
by definition, at the front of the pipeline, it strives to empty its FIFO as fast as possible.
X-Ref Target - Figure 4-6
Figure 4-6:
Pointer Format for a 32 Location FIFO
