Xilinx LogiCORE IP Spartan-6 Getting Started Manual Download Page 51 | Manualshive

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Xilinx LogiCORE IP Spartan-6 Getting Started Manual Download Page 51

Spartan-6 FPGA GTP Transceiver Wizard v1.8

51

UG546 (v1.8) December 14, 2010

Example Design Hierarchy

the wrapper. The RX_SYNC module demonstrates the RX phase-alignment procedure
outlined in the

Spartan-6 FPGA GTP Transceivers User Guide

.

The example design also demonstrates how to properly connect clocks to GTX transceiver
ports TXUSRCLK, TXUSRCLK2, RXUSRCLK and RXUSRCLK2. Properly configured
DCM (Digital Clock manager), PLL (Phase lock loop) wrappers are also provided if they
are required to generate user clocks for the instantiated GTP transceivers.

The example design may be synthesized using XST or Synplify Pro, implemented with
ISE® software and then observed in hardware using the Chipscope Pro tools. RX output
ports such as RXDATA can be observed on the ChipScope Pro ILA core while input ports
can be controlled from the ChipScope Pro VIO core. A ChipScope Pro project file is also
included with each example design.

For the example design to work properly in simulation or in hardware, both the transmit
and receive side need to be configured with the same line rate, encoding and datapath
width in the GUI.

Example Design Hierarchy

The hierarchy for the design used in this example is as follows:

example_tb

|___example_mgt_top

|___mgt_userclk_source_pll

|___ibufds

|___frame_gen

|___frame_check

|___pcie_wrapper

|___pcie_wrapper_tile

|___gtpa1_dual

«
...
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Summary of Contents for LogiCORE IP Spartan-6

Page 1: ...LogiCORE IP Spartan 6 FPGA GTP Transceiver Wizard v1 8 Getting Started Guide UG546 v1 8 December 14 2010...

Page 2: ...but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx 2009 2010 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other design...

Page 3: ...ent 11 Chapter 2 Installation and Licensing System Requirements 13 Before You Begin 13 Installing the Wizard 14 Verifying Your Installation 14 Chapter 3 Running the Wizard Overview 15 Setting Up the P...

Page 4: ...Simulator 43 Using ChipScope Pro Cores with the Spartan 6 FPGA GTP Transceiver Wizard Core 43 Chapter 5 Detailed Example Design Directory and File Structure 45 Directory and File Contents 46 project d...

Page 5: ...to generate a sample GTP transceiver wrapper with the Xilinx CORE Generator tool Chapter 4 Quick Start Example Design introduces the example design that is included with the GTP Transceiver wrappers T...

Page 6: ...s drawn so that it overlaps the pin of a symbol the two nets are not connected Dark Shading Items that are not supported or reserved This feature is not supported Square brackets An optional entry or...

Page 7: ...entions are used in this document Convention Meaning or Use Example Blue text Cross reference link to a location in the current document See the section Additional Resources for details Refer to Title...

Page 8: ...8 www xilinx com Spartan 6 FPGA GTP Transceiver Wizard v1 8 UG546 v1 8 December 14 2010 Preface About This Guide...

Page 9: ...addition the example design delivered with the core is provided in Verilog or VHDL The Wizard produces a wrapper that instantiates one or more properly configured GTP transceivers for custom applicati...

Page 10: ...ion and updates about the Spartan 6 FPGA GTP Transceiver Wizard see the following documents located at the Architecture Wizard page DS713 Spartan 6 FPGA GTP Transceiver Wizard v1 8 Data Sheet Spartan...

Page 11: ...correctly Document For comments or suggestions about this document please submit a WebCase from www xilinx com support Registration is required to log in to WebCase Be sure to include the following i...

Page 12: ...12 www xilinx com Spartan 6 FPGA GTP Transceiver Wizard v1 8 UG546 v1 8 December 14 2010 Chapter 1 Introduction...

Page 13: ...v12 4 Mentor Graphics ModelSim 6 5c Cadence Incisive Enterprise Simulator IES 9 2 Synopsys VCS and VCS MX 2009 12 Synopsys Synplify Pro D 2010 03 Check the release notes for the required Service Pack...

Page 14: ...n 6 FPGA GTP Transceiver Wizard in the CORE Generator tool 1 Start the CORE Generator tool 2 The IP core functional categories appear at the left side of the window as shown in Figure 2 1 3 Click to e...

Page 15: ...of the following components A single GTP transceiver wrapper implementing a four lane PCI EXPRESS interface using four GTP transceivers A demonstration test bench to drive the example design in simula...

Page 16: ...e example project first create a directory using the following steps 1 Change directory to the desired location This example uses the following location and directory name Projects pcie_example 2 Star...

Page 17: ...list This example uses the XC6SLX45T device see Figure 3 3 Note If an unsupported silicon family is selected the Spartan 6 FPGA GTP Transceiver Wizard remains light grey in the taxonomy tree and cann...

Page 18: ...rting files including the example design are generated in the project directory For additional details about the example design files and directories see Implementing the Example Design page 41 1 Loca...

Page 19: ...vers and the reference clock source 1 In the Component Name field enter a name for the core instance This example uses the name pcie_wrapper The number of GTPA1_DUAL transceiver primitives appearing o...

Page 20: ...share a single reference clock signal The PCI EXPRESS example uses the REFCLK X0Y0 signal from the upper pair of selected primitives GTP1 REFCLK Same as above for the GTP1 transceiver Advanced Clockin...

Page 21: ...ded The remaining options are divided into GTP0 and GTP1 groups with identical parameters These apply to the two GTP transceivers present in each GTPA1_DUAL primitive The remaining discussion in this...

Page 22: ...er prior to transmission Data Path Width 8 Sets both the internal transmitter data path and the transmitter application interface data path width to a single 8 bit byte 10 Sets the internal transmitte...

Page 23: ...a single 10 bit byte If 8B 10B encoding is selected the receiver application interface data path width will be set to 8 bits 16 Sets the internal receiver data path width to a single 8 bit byte Sets t...

Page 24: ...XCHARDISPMODE Two bit wide ports control disparity of outgoing 8B 10B data High order bit affects high order byte of data path TXCHARDISPVAL TXKERR Two bit wide port flags invalid K character codes as...

Page 25: ...source signal options and Table 3 9 lists the optional ports The Enable TX buffer setting controls whether the TX buffer is enabled or bypassed See the Spartan 6 FPGA GTP Transceivers User Guide for d...

Page 26: ...hase Alignment Circuit is used RXRECCLK RXUSRCLK is driven by RXRECCLK This option is required if the RX Phase Alignment Circuit is used REFCLKOUT RXUSRCLK is driven by REFCLKOUT This option is not av...

Page 27: ...ther TXUSRCLK or RXUSRCLK This option is not available when the TX Phase Alignment circuit is used TXRESET Active High reset signal for the transmitter PCS logic TXBUFSTATUS Two bit signal monitors th...

Page 28: ...rresponding bit in the comma patterns is to be matched A 0 bit indicates don t care for the corresponding bit in the comma patterns The PCI EXPRESS example matches all ten bits 1111111111 Align to Any...

Page 29: ...proximately 45 Selecting Use TXPREEMPHASIS port enables the optional TXPREEMPHASIS configuration port to dynamically set the pre emphasis level The PCI EXPRESS example uses the default setting of 000...

Page 30: ...gain Table 3 14 RX Termination Option Description Disable Internal AC Coupling Bypasses the internal AC coupling capacitor Use this option for DC coupling applications or for external AC coupling Term...

Page 31: ...Loss of Sync Page 7 Table 3 16 OOB Signal Detection Option Description Use RX OOB Signal Detection Enables the internal Out of Band signal detector OOB OOB signal detection is used for PCI EXPRESS and...

Page 32: ...rs into the bit stream Table 3 18 Loss of Sync State Machine Option Description RXLOSSOFSYNC Optional Port Two bit multi purpose status port The meaning of the bits is determined by the settings below...

Page 33: ...X PCI Express SATA Features The RX PCI Express SATA Features screen page 8 of the Wizard Figure 3 12 configures the receiver for PCI EXPRESS and Serial ATA SATA features Table 3 19 page 34 details the...

Page 34: ...ing This option should be activated whenever the transceiver is used for PCI EXPRESS This option is not available if RXSTATUS encoding format is set to SATA SATA TX COM Sequence Bursts Integer value b...

Page 35: ...down control signal RXSTATUS 3 bit receiver status signal The encoding of this signal is dependent on the setting of RXSTATUS encoding format RXVALID Active High PCI Express RX OOB Beacon signal Indic...

Page 36: ...correction parameters Also the common channel bonding sequence is defined on this page The Channel Bonding settings and sequence definition are common between both transceivers of each selected pair...

Page 37: ...Sequence 1 Max Skew Select from the drop down list the maximum skew in characters that can be handled by channel bonding Must always be less than the minimum distance between channel bonding sequence...

Page 38: ...RESS example uses 1 Rx Buffer Max Latency Select from the drop down list the maximum number of characters to permit in the receive buffer before clock correction attempts to delete incoming clock corr...

Page 39: ...rn the protocol requires The PCI EXPRESS sequence length is 8 bits 00011100 is used for the first symbol of sequence 1 The remaining symbols are disabled because the Sequence length is set to 1 K Char...

Page 40: ...2010 Chapter 3 Running the Wizard Summary The Summary screen page 11 of the Wizard Figure 3 15 provides a summary of the selected configuration parameters After reviewing the settings click Generate t...

Page 41: ...roceeds and the generated output populates the appropriate subdirectories The directory structure for the PCI EXPRESS example is provided in Chapter 5 Detailed Example Design After wrapper generation...

Page 42: ...tation for instructions on how to compile ISE simulation libraries The Wizard provides a command line script for use within ModelSim To run a VHDL or Verilog ModelSim simulation of the wrapper use the...

Page 43: ...ctory component_name simulation functional 2 Launch the simulation script For Windows simulate_isim bat For Linux simulate_isim sh The ISim script compiles the example design and test bench and adds t...

Page 44: ...44 www xilinx com Spartan 6 FPGA GTP Transceiver Wizard v1 8 UG546 v1 8 December 14 2010 Chapter 4 Quick Start Example Design...

Page 45: ...he operation of the demonstration test bench Directory and File Structure project directory topdirectory Top level project directory name is user defined project directory component name opdirectory C...

Page 46: ...o GTP Wrapper files instantiation templates Includes templates for the GTP Wrapper module the IBUFDS and essential GTP support modules such as TX_SYNC component_name xco Log file from the CORE Generat...

Page 47: ...Guide Back to Top Table 5 4 Example Design Directory Name Description project_dir component_name example_design frame_check v hd Frame check logic to be instantiated in the example design frame_gen v...

Page 48: ...nt bat A Windows batch file that processes the example design through the Xilinx tool flow implement sh A Linux shell script that processes the example design through the Xilinx tool flow implement_sy...

Page 49: ...model Back to Top Table 5 8 Functional Directory Name Description project_dir component_name simulation functional simulate_isim sh Linux script for running simulation using ISE Simulator simulate_isi...

Page 50: ...ting pattern The frame check works by first scanning the received data for the START_OF_PACKET_CHAR In 8B 10B designs this is the comma alignment character Once the START_OF_PACKET_CHAR has been found...

Page 51: ...gn may be synthesized using XST or Synplify Pro implemented with ISE software and then observed in hardware using the Chipscope Pro tools RX output ports such as RXDATA can be observed on the ChipScop...

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