10GBASE-KR Ethernet TRD
68
UG1058 (v2017.1) April 19, 2017
Chapter 5:
Reference Design Details
the end of the packet (rx_tlast) 14 bytes of header are subtracted from the count to get
payload count.
• RX Packet Count. This counter counts the number of received packets. The counter
increments when rx_tvalid and rx_tready and rx_tlast signal are asserted.
The counts are truncated to a four-byte resolution, and the last two bits of the register
indicate the sampling period. The last two bits transition every second from
00
to
01
to
10
to
11
. The software polls the performance registers every second. If the sampling bits are
the same as the previous read, then the software needs to discard the second read and try
again. When the one-second timer expires, the new byte counts are loaded into the
registers, overwriting the previous values.
shows the parameters and ports on this
module.
Table 5-3:
Ethernet Performance Monitor Parameters and Ports
Port/Parameter Name
Type
Description
ONE_SEC_CLOCK_COUNT Parameter Defines the number of 156.25 MHz clock cycles equivalent to 1 sec.
Default value is
32'h9502F90
.
Clock and Reset Ports
reset
Input
Synchronous reset.
clk
Input
156.25 MHz clock.
Transmit Ports on the AXI4-Stream Interface
tx_axis_tdata[63:0]
Input
Data to be transmitted to the 10-Gigabit Ethernet MAC IP core.
tx_axis_tkeep[7:0]
The transmit keep signal is used to determine which data bytes are valid
on tx_axis_tdata during a given beat (this signal is valid only if
tx_axis_tvalid and tx_axis_tready are both asserted).
Bit 0 corresponds to the least significant byte on tx_axis_tdata and bit 7
corresponds to the most significant byte. When tx_axis_tlast is not
asserted, the only valid value is
0xFF
.
When tx_axis_tlast is asserted, valid values are
0x01
,
0x03
,
0x07
,
0x0F
,
0x1F
,
0x3F
,
0x7F
, and
0xFF
.
tx_axis_tlast
Input
End of frame indicator on transmit packets. Valid only along with
assertion of tx_axis_tvalid.
tx_axis_tvalid
Input
Source ready to provide transmit data. Indicates that the generator is
presenting valid data on tx_axis_tdata.
tx_axis_tuser
Input
If asserted indicates an underrun frame. This is tied to
1'b0
.
tx_axis_tready
Input
Destination ready for transmit. Indicates that the 10-Gigabit Ethernet
MAC IP core is ready to accept data on tx_axis_tdata.
The simultaneous assertion of tx_axis_tvalid and tx_axis_tready marks the
successful transfer of one data beat on tx_axis_tdata.
Receive Ports on the AXI4-Stream Interface
rx_axis_tdata[63:0]
Input
Data received by the 10-Gigabit Ethernet MAC IP core.
