Xilinx KCU1250 10GBASE-KR, User Manual

Page: 66 / 91

10GBASE-KR Ethernet TRD 66
UG1058 (v2017.1) April 19, 2017 www.xilinx.com
Chapter 5: Reference Design Details
The source and destination MAC addresses are parameters into this block. The length field
is the data payload value. The actual length of a packet generated by this block is:
• 14 bytes of header (Destination A Source A Length/Type Field) +
Data payload
The sequence number field indicates packet count and increments by one every packet.
The generated packets are transmitted on AXI4-Stream interface to the 10-Gigabit Ethernet
MAC IP core. Table 5-2 shows the parameters and ports on the generator module.
Table 5-1: Packet Format of Generated Packets
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Source Address Destination Address
Sequence Number Length Source Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequence Number Sequence Number
Sequence Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-2: Generator Module Parameters and Ports
Port/Parameter Name Type Description
XIL_MAC_ID_THIS Parameter
Source MAC Address
For channel 0 =
48'h111100000000
For channel 1 =
48'h222200000000
XIL_MAC_ID_OTHER Parameter
Destination MAC Address
For channel 0 =
48'h222200000000
For channel 1 =
48'h111100000000
Clock and Reset Ports
reset Input Synchronous reset.
tx_axis_clk Input 156.25 MHz clock transmit ports on the AXI4-Stream interface.
Transmit Ports on the AXI4-Stream Interface
tx_axis_tdata[63:0] Output Data to be transmitted to the 10-Gigabit Ethernet MAC IP core.
tx_axis_tkeep[7:0]
The transmit keep signal is used to determine which data bytes are valid
on tx_axis_tdata during a given beat (this signal is valid only if
tx_axis_tvalid and tx_axis_tready are both asserted).
Bit 0 corresponds to the least significant byte on tx_axis_tdata and bit 7
corresponds to the most significant byte.
When tx_axis_tlast is not asserted, the only valid value is
0xFF
. When
tx_axis_tlast is asserted, valid values are
0x1
,
0x3
,
0x7
,
0xf
,
0x1f, 0x3f
,
0x7f
and
0xff
.
tx_axis_tlast Output
End of frame indicator on transmit packets. Valid only along with assertion
of tx_axis_tvalid.
tx_axis_tvalid Output
Source ready to provide transmit data. Indicates that the generator is
presenting valid data on tx_axis_tdata.
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