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Xilinx KC705, User Manual

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Xilinx KC705 User Manual Download Page 69

KC705 Evaluation Board

www.xilinx.com

69

UG810 (v1.3) May 10, 2013

Configuration Options

Configuration Options

The FPGA on the KC705 board can be configured by the following methods:

•

Master BPI (uses the Linear BPI Flash).

•

Master SPI (uses the Quad-SPI Flash).

•

JTAG (uses the USB-to-JTAG Bridge or Download cable). See 

USB JTAG Module, 

page 22

 for more information

See 

UG470

, 

7 Series FPGAs Configuration User Guide

 for details on configuration modes.

The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0) 
settings selected through DIP switch SW13. 

Table 1-35

 lists the supported mode switch 

settings.

Figure 1-39

 shows mode switch SW13.

The mode pins settings on SW13 determine if the Linear BPI Flash or the Quad SPI Flash is 
used for configuring the FPGA. DIP switch SW13 also provides the upper two address bits 
for the Linear BPI Flash and can be used to select one of multiple stored configuration 
bitstreams. 

Figure 1-40

 shows the connectivity between the onboard non-volatile Flash 

devices used for configuration and the FPGA.

To obtain the fastest configuration speed an external 66 MHz oscillator is wired to the 
EMCCLK pin of the FPGA. This allows users to create bitstreams that will configure the 

Table 1-35: 

Mode Switch SW13 Settings 

Configuration

Mode

Mode Pins (M[2:0])

Bus

Width

CCLK

Direction

Master SPI

001

x1, x2, x4

Output

Master BPI

010

x8, x16

Output

JTAG

101

x1

Not Applicable

X-Ref Target - Figure 1-39

Figure 1-39: 

Mode Switch

UG810_c1_32_120511

SDA05H1SBD

SW13

R401
220

Ω

0.1 W
1%

R402
220

Ω

0.1 W
1%

VCC2V5

FPGA_M2

FPGA_M1

FPGA_M0

FLASH_A25

FLASH_A24

R396
1.21k

Ω

0.1 W
1%

R397
1.21k

Ω

0.1 W
1%

R398
1.21k

Ω

0.1 W
1%

R399
1.21k

Ω

0.1 W
1%

R400
1.21k

Ω

0.1 W
1%

1

2

3

4

5

10

9

8

7

6

GND

ON

Summary of Contents for KC705

Page 1: ...KC705 Evaluation Board for the Kintex 7 FPGA User Guide UG810 v1 3 May 10 2013 ...

Page 2: ...press PCIe and PCI X are trademarks of PCI SIG All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 01 23 12 1 0 Initial Xilinx release 04 05 12 1 1 Updated links from Table 1 1 page 8 Revised the JTAG configuration mode USB cable description under FPGA Configuration page 9 Added Enc...

Page 3: ...r 34 10 100 1000 Tri Speed Ethernet PHY 36 USB to UART Bridge 39 HDMI Video Output 40 LCD Character Display 43 I2C Bus Switch 45 Status LEDs 46 Ethernet PHY Status LEDs 47 User I O 47 Switches 52 FPGA Mezzanine Card Interface 54 Power Management 61 XADC Header 66 Configuration Options 69 Appendix A Default Switch and Jumper Settings DIP Switch SW11 User GPIO 71 DIP Switch SW13 Mode and Flash Addre...

Page 4: ...tal 85 Temperature 85 Humidity 85 Operating Voltage 85 Appendix F Additional Resources Xilinx Resources 87 Solution Centers 87 Further Resources 87 References 88 Appendix G Regulatory and Compliance Information Declaration of Conformity 89 Directives 89 Standards 89 Electromagnetic Compatibility 89 Safety 90 Markings 90 ...

Page 5: ...s are provided See KC705 Board Features for a complete list of features The details for each feature are described in Feature Descriptions page 7 Additional Information See Appendix F Additional Resources for references to documents files and resources relevant to the KC705 board KC705 Board Features Kintex 7 XC7K325T 2FFG900C FPGA 1 GB DDR3 memory SODIMM 128 MB Linear BPI Flash memory 128 Mb Quad...

Page 6: ...MC LPC connector SFP connector I2C programmable jitter attenuating precision clock multiplier Status LEDs Ethernet status Power good FPGA INIT FPGA DONE User I O USER LEDs eight GPIO User pushbuttons five directional CPU reset pushbutton User DIP switch 4 pole GPIO User edge drive rotary encoder switch User SMA GPIO connectors one pair LCD character display 16 characters x 2 lines Switches Power o...

Page 7: ...h numbered feature that is referenced in Figure 1 2 is described in the sections that follow Note The image in Figure 1 2 is for reference only and might not reflect the current revision of the board X Ref Target Figure 1 1 Figure 1 1 KC705 Board Block Diagram UG810_c1_01_011812 Kintex 7 FPGA XC7K325T 2FFG900C 128 MB Linear BPI Flash memory 128 Mb Quad SPI Flash Memory 8 lane PCI Express Edge Conn...

Page 8: ... shield Micron MT8JTF12864HZ 1G6G1 15 3 U58 Linear BPI Flash Memory Micron Numonyx PC28F00AP30TF 26 4 U7 Quad SPI Flash Memory Micron Numonyx N25Q128A13BSF40F 26 5 U9 SD Card Interface Molex 67840 8001 28 6 USB JTAG Module Digilent USB JTAG Module with micro B receptacle 14 7 U6 System Clock Source back side of board SiTime SIT9102 243N25E200 0000 23 8 U45 Programmable User Clock Source back side ...

Page 9: ...EDs EPHY status LED dual green 25 34 DS14 DS20 DS24 Status LEDs Status LEDs green 29 22 DS1 DS4 Ds10 DS25 DS27 User GPIO LEDs GPIO LEDs green 29 23 SW2 SW6 User Pushbuttons E Switch TL3301EP100QG 29 24 SW11 GPIO DIP Switch C and K 4 pole SDA05H1SBD 29 25 SW8 Rotary Switch Panasonic EVQ WK4001 29 26 J13 J14 GPIO SMA Connectors Rosenberger 32K10K 400L5 23 27 SW15 Power On Off Slide Switch SW15 C and...

Page 10: ... rechargeable 1 5V lithium button type battery B1 is soldered to the board with the positive output connected to FPGA U1 VCCBATT pin C10 The battery supply current IBATT specification is 150 nA max when board power is off B1 is charged from the VCCAUX_IO 2 0V rail through a series diode with a typical forward voltage drop of 0 38V and 4 7 KΩ current limit resistor The nominal charging voltage is 1...

Page 11: ...D11 40V 200 mW NC FPGA_VBATT VCCAUX_IO 2 0V R406 4 70K 1 1 16W To FPGA U1 Pin C10 VCCBATT Table 1 3 I O Voltage Rails U1 FPGA Bank Power Supply Rail Net Name Voltage Bank 0 VCC2V5_FPGA 2 5V Bank 12 1 VADJ_FPGA 2 5V default Bank 13 1 VADJ_FPGA 2 5V default Bank 14 VCC2V5_FPGA 2 5V Bank 15 VCC2V5_FPGA 2 5V Bank 16 1 VADJ_FPGA 2 5V default Bank 17 1 VADJ_FPGA 2 5V default Bank 18 1 VADJ_FPGA 2 5V def...

Page 12: ...stor connection An external 0 75V reference VTTREF is provided for data interface banks 32 and 34 Any interface connected to these banks that requires a reference voltage must use this FPGA voltage reference The connections between the DDR 3 memory and the FPGA are listed in Table 1 4 Table 1 4 DDR3 Memory Connections to the FPGA U1 FPGA Pin Net Name J1 DDR3 Memory Pin Number Pin Name AH12 DDR3_A0...

Page 13: ...D13 24 DQ13 AE18 DDR3_D14 34 DQ14 AD18 DDR3_D15 36 DQ15 AG19 DDR3_D16 39 DQ16 AK19 DDR3_D17 41 DQ17 AG18 DDR3_D18 51 DQ18 AF18 DDR3_D19 53 DQ19 AH19 DDR3_D20 40 DQ20 AJ19 DDR3_D21 42 DQ21 AE19 DDR3_D22 50 DQ22 AD19 DDR3_D23 52 DQ23 AK16 DDR3_D24 57 DQ24 AJ17 DDR3_D25 59 DQ25 AG15 DDR3_D26 67 DQ26 AF15 DDR3_D27 69 DQ27 AH17 DDR3_D28 56 DQ28 AG14 DDR3_D29 58 DQ29 AH15 DDR3_D30 68 DQ30 AK15 DDR3_D31 ...

Page 14: ...D44 146 DQ44 AJ4 DDR3_D45 148 DQ45 AK1 DDR3_D46 158 DQ46 AJ1 DDR3_D47 160 DQ47 AF1 DDR3_D48 163 DQ48 AF2 DDR3_D49 165 DQ49 AE4 DDR3_D50 175 DQ50 AE3 DDR3_D51 177 DQ51 AF3 DDR3_D52 164 DQ52 AF5 DDR3_D53 166 DQ53 AE1 DDR3_D54 174 DQ54 AE5 DDR3_D55 176 DQ55 AC1 DDR3_D56 181 DQ56 AD3 DDR3_D57 183 DQ57 AC4 DDR3_D58 191 DQ58 AC5 DDR3_D59 193 DQ59 AE6 DDR3_D60 180 DQ60 AD6 DDR3_D61 182 DQ61 AC2 DDR3_D62 ...

Page 15: ...DR3_DQS3_N 62 DQS3_N AH16 DDR3_DQS3_P 64 DQS3_P AJ7 DDR3_DQS4_N 135 DQS4_N AH7 DDR3_DQS4_P 137 DQS4_P AH1 DDR3_DQS5_N 152 DQS5_N AG2 DDR3_DQS5_P 154 DQS5_P AG3 DDR3_DQS6_N 169 DQS6_N AG4 DDR3_DQS6_P 171 DQS6_P AD1 DDR3_DQS7_N 186 DQS7_N AD2 DDR3_DQS7_P 188 DQS7_P AD8 DDR3_ODT0 116 ODT0 AC10 DDR3_ODT1 120 ODT1 AK3 DDR3_RESET_B 30 RESET_B AC12 DDR3_S0_B 114 S0_B AE8 DDR3_S1_B 121 S1_B AJ9 DDR3_TEMP_...

Page 16: ...t the 33 MHz data rate supported by the PC28F00AP30TF Flash memory by using a configuration bitstream generated with bitgen options for synchronous configuration and for configuration clock division The fastest configuration method uses the external 66 MHz oscillator connected to the FPGA EMCCLK pin with a bitstream that has been built to divide the configuration clock by two The division is neces...

Page 17: ..._A6 C2 A7 W24 FLASH_A7 A3 A8 W23 FLASH_A8 B3 A9 V20 FLASH_A9 C3 A10 V19 FLASH_A10 D3 A11 W26 FLASH_A11 C4 A12 V25 FLASH_A12 A5 A13 V30 FLASH_A13 B5 A14 V29 FLASH_A14 C5 A15 V27 FLASH_A15 D7 A16 P22 FLASH_A16 D8 A17 P21 FLASH_A17 A7 A18 N24 FLASH_A18 B7 A19 N22 FLASH_A19 C7 A20 N21 FLASH_A20 C8 A21 N20 FLASH_A21 A8 A22 N19 FLASH_A22 G1 A23 N26 FLASH_A23 H8 A24 M23 FLASH_A24 B6 A25 M22 FLASH_A25 B8 ...

Page 18: ...configuration mode Figure 1 5 shows the connections of the linear BPI Flash memory on the KC705 board For more information about the Numonyx PC28F00AP30TF see Ref 5 T22 FLASH_D6 G6 DQ6 T23 FLASH_D7 H7 DQ7 U20 FLASH_D8 E1 DQ8 P29 FLASH_D9 E3 DQ9 R29 FLASH_D10 F3 DQ10 P27 FLASH_D11 F4 DQ11 P28 FLASH_D12 F5 DQ12 T30 FLASH_D13 H5 DQ13 P26 FLASH_D14 G7 DQ14 R26 FLASH_D15 E7 DQ15 U29 FLASH_WAIT F7 WAIT ...

Page 19: ... FLASH_A12 A13 FLASH_A13 A14 FLASH_A14 A15 FLASH_A15 A16 FLASH_A16 A17 FLASH_A17 A18 FLASH_A18 A19 FLASH_A19 A20 FLASH_A20 A21 FLASH_A21 A22 FLASH_A22 A23 FLASH_A23 A24 FLASH_A24 A25 FLASH_A25 A26 NC A27 VCC2 VCCQ1 VCCQ2 VCCQ3 VPP VCC1 FLASH_D0_R DQ0 FLASH_D1_R DQ1 FLASH_D2_R DQ2 FLASH_D3_R DQ3 FLASH_D4_R DQ4 FLASH_D5_R DQ5 FLASH_D6_R DQ6 FLASH_D7_R DQ7 FLASH_D8_R DQ8 FLASH_D9_R DQ9 FLASH_D10_R DQ...

Page 20: ... SPI Flash memory on the KC705 board For more information about the Numonyx N25Q128A13BSF40F see Ref 5 SD Card Interface Figure 1 2 callout 5 Table 1 6 Quad SPI Flash Memory Connections to the FPGA U1 FPGA Pin Net Name U7 Quad SPI Flash Memory Pin Number Pin Name P24 FLASH_D0 15 DQ0 R25 FLASH_D1 8 DQ1 R20 FLASH_D2 9 DQ2 R21 FLASH_D3 1 DQ3 B10 FPGA_CCLK 16 C U19 QSPI_IC_CS_B 1 7 S_B Notes 1 FPGA_FC...

Page 21: ... B8 OE GND SDIO Card Connector U9 DETECT DAT2 DAT1 DAT0 CLK CMD CD_DAT3 VDD PROTECT GNDTAB2 VSS1 GNDTAB1 VSS2 GND GND SDIO_SDWP 11 SDIO_SDDET 10 SDIO_DAT2 9 SDIO_DAT1 8 SDIO_DAT0 7 SDIO_CLK 5 SDIO_CMD 1 SDIO_CD_DAT3 VCC3V3 C22 0 1μF 25V X5R GND 4 6 3 D_P NC 12 GNDTAB3 GNDTAB4 IOGND1 IOGND2 15 16 17 18 13 14 51 1K 1 Six Places VCC3V3 R457 R458 R455 R456 R453 R454 2 VADJ C543 0 1μF 25V X5R GND GND V...

Page 22: ...an FMC mezzanine card is attached Switch U76 adds an attached FMC HPC mezzanine card to the FPGAs JTAG chain as determined by the FMC_HPC_PRSNT_M2C_B signal Switch U77 adds an attached FMC HPC mezzanine card to the FPGAs JTAG chain as determined by the FMC_LPC_PRSNT_M2C_B signal The attached FMC card must implement a TDI to TDO connection via a device or bypass jumper for the JTAG chain to be comp...

Page 23: ...nector TDI TDO J22 TMS TCK PRSNT_L VCC3V3 FMC LPC Connector TDI TDO J2 TMS TCK PRSNT_L Kintex 7 FPGA TDI TDO U1 TMS TCK Digilent USB JTAG Module TMS TDI SN74AVC1T45 Voltage Translator U102 SN74AVC2T45 Voltage Translator U69 SN74LV541A Voltage Translator U5 R381 15Ω U59 R382 15Ω R380 15Ω TCK TDO TMS TDI J60 TCK TDO JTAG Header VCC2V5 VCC2V5 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 U76 U77 Table 1 8 KC705...

Page 24: ... 10 User SMA Clock differential pair J11 USER_SMA_CLOCK_P net name See User SMA Clock Input page 27 J12 USER_SMA_CLOCK_N net name See User SMA Clock Input page 27 GTX SMA REF Clock differential pair J16 SMA_MGT_REFCLK_P net name See GTX SMA Clock Input page 27 J15 SMA_MGT_REFCLK_N net name See GTX SMA Clock Input page 27 Jitter Attenuated Clock U70 Si5324C LVDS precision clock multiplier jitter at...

Page 25: ...he KC705 board will revert the user clock to its default frequency of 156 250 MHz Programmable Oscillator Silicon Labs Si570BAB0000544DG 10 MHz 810 MHz Differential Output I2 C address 0x5D The user clock circuit is shown in Figure 1 11 For more information about the Silicon Labs Si570 see Ref 8 X Ref Target Figure 1 10 Figure 1 10 System Clock Source UG810_c1_09_120211 GND VCC2V5 SIT9102 200 MHz ...

Page 26: ...er 1 KC705 Evaluation Board Features Reference design files are available to demonstrate how to program the Si570 programmable oscillator See XTP186 KC705 Si570 Programming RDF0175 Reference Design Files XTP187 KC705 Si570 Fixed Frequencies RDF0176 Reference Design Files ...

Page 27: ...ut 10 The KC705 board includes a pair of SMA connectors for a GTX clock wired to GTX Quad bank 117 This differential clock has signal names SMA_MGT_REFCLK_P and SMA_REFCLK_N which are connected to FPGA U1 pins J8 and J7 respectively Figure 1 13 shows this AC coupled clock circuit External user provided GTX reference clock on SMA input connectors Differential Input X Ref Target Figure 1 12 Figure 1...

Page 28: ... to drive the reference clock inputs of a GTX transceiver The jitter attenuated clock circuit is shown in Figure 1 14 For more information about the Silicon Labs Si5324 see Ref 8 X Ref Target Figure 1 14 Figure 1 14 Jitter Attenuated Clock UG810_c1_13_101012 R424 4 7KΩ 5 SI5326_VCC Si5324C C GM Clock Multiplier Jitter Attenuator VDDA GND XB XA NC5 32 6 5 29 28 U70 CKOUT1_N 7 8 CKOUT1_P C473 0 1μF ...

Page 29: ...ove or Quad below the GTX Quad of interest There are four GTX Quads on the KC705 board with connectivity as shown here Quad 115 No directly wired GTX input reference clocks Contains 4 GTX transceivers for PCI Express lanes 4 7 Quad 116 MGTREFCLK0 Si5324 jitter attenuator MGTREFCLK1 PCIe edge connector clock Contains 4 GTX transceivers for PCIe lanes 0 3 Quad 117 MGTREFCLK0 SGMII clock MGTREFCLK1 S...

Page 30: ...oard supports up to Gen2 x8 The PCIe clock is input from the edge connector It is AC coupled to the FPGA through the MGTREFCLK1 pins of Quad 115 PCIE_CLK_Q0_P is connected to FPGA U1 pin U8 and the _N net is connected to pin U7 The PCI Express clock circuit is shown in Figure 1 15 MGT_BANK_116 GTXE2_CHANNEL_X0Y4 PCIe3 GTXE2_CHANNEL_X0Y5 PCIe2 GTXE2_CHANNEL_X0Y6 PCIe1 GTXE2_CHANNEL_X0Y7 PCIe0 MGTRE...

Page 31: ... pair GTXE2_CHANNEL_X0Y6 PCIE_RX1_N P5 B20 PETn1 Integrated Endpoint block receive pair GTXE2_CHANNEL_X0Y6 PCIE_RX2_P R4 B23 PETp2 Integrated Endpoint block receive pair GTXE2_CHANNEL_X0Y5 PCIE_RX2_N R3 B24 PETn2 Integrated Endpoint block receive pair GTXE2_CHANNEL_X0Y5 PCIE_RX3_P T6 B27 PETp3 Integrated Endpoint block receive pair GTXE2_CHANNEL_X0Y4 PCIE_RX3_N T5 B28 PETn3 Integrated Endpoint blo...

Page 32: ...2_CHANNEL_X0Y0 PCIE_TX7_N Y1 A48 PERn7 Integrated Endpoint block transmit pair GTXE2_CHANNEL_X0Y0 PCIE_CLK_QO_P U8 A13 REFCLK Integrated Endpoint block differential clock pair from PCIe MGT_BANK_115 PCIE_CLK_QO_N U7 A14 REFCLK Integrated Endpoint block differential clock pair from PCIe MGT_BANK_115 PCIE_PRSNT_B J32 2 4 6 A1 PRSNT 1 J42 Lane Size Select jumper NA PCIE_WAKE_B F23 B11 WAKE Integrated...

Page 33: ... 116 to PCIe Edge Connector Connections Quad 116 Pin Name FPGA Pin U1 Schematic Net Name PCIe Edge Connector Pin PCIe Edge in Name FFG900 Placement MGTXTXP0_116_P2 P2 PCIE_TX3_P A29 PERp3 GTXE2_CHANNEL_X0Y4 MGTXTXN0_116_P1 P1 PCIE_TX3_N A30 PERn3 GTXE2_CHANNEL_X0Y4 MGTXRXP0_116_T6 T6 PCIE_RX3_P B27 PETp3 GTXE2_CHANNEL_X0Y4 MGTXRXN0_116_T5 T5 PCIE_RX3_N B28 PETn3 GTXE2_CHANNEL_X0Y4 MGTXTXP1_116_N4 ...

Page 34: ...re 1 2 callout 14 The KC705 board contains a small form factor pluggable SFP connector and cage assembly that accepts SFP or SFP modules Figure 1 17 shows the SFP module connector circuitry MGTREFCLK1P_116_N8 N8 FMC_LPC_GBTCLK0_M2C_C_P MGT_BANK_116 MGTREFCLK1N_116_N7 N7 FMC_LPC_GBTCLK0_M2C_C_N MGT_BANK_116 Table 1 13 GTX Quad 116 to PCIe Edge Connector Connections Cont d Quad 116 Pin Name FPGA Pin...

Page 35: ...26 27 28 29 30 19 18 16 15 13 12 8 20 17 14 10 11 1 7 9 6 5 4 3 2 31 P5 SFP Module Connector 74441 0010 SFP_LOS SFP_TX_FAULT SFP_IIC_SDA SFP_IIC_SCL SFP_RX_P SFP_RX_N SFP_TX_P SFP_TX_DISABLE_TRANS SFP_RS0 3 2 1 J27 J28 1 2 J4 HDR_1X2 SFP_MOD_DETECT 1 J9 SFP_TX_N SFP_VCCR R552 4 7KΩ L4 4 7μH 3 0 A VCC3V3 C28 0 1μF GND VCC3V3 L3 4 7μH 3 0 A C587 22μF C29 0 1μF C55 22μF GND 1 Q2 NDS331N 460 mW SFP_TX...

Page 36: ...RANS 3 TX_DISABLE Notes 1 On KC705 boards prior to Rev 1 1 SFP connector P5 pin 18 TD_P is connected to net SFP_TX_N and pin 19 TD_N is connected to net SFP_TX_P Table 1 15 SFP Module Control and Status SFP Control Status Signal Board Connection SFP_TX_FAULT Test Point J10 High Fault Low Normal Operation SFP_TX_DISABLE Jumper J4 Off FP Disabled On SFP Enabled SFP_MOD_DETECT Test Point J9 High Modu...

Page 37: ...lock input of the FPGA to set the common mode voltage Figure 1 18 shows the Ethernet SGMII clock source Table 1 16 PHY Default Interface Mode Mode Jumper Settings J29 J30 J64 GMII MII to copper default Jumper over pins 1 2 Jumper over pins 1 2 No jumper SGMII to copper no clock Jumper over pins 2 3 Jumper over pins 2 3 No jumper RGMII Jumper over pins 1 2 No jumper Jumper on Table 1 17 Board Conne...

Page 38: ...MIICLK_XTAL_OUT GND2 GND2 X2 X1 X3 25 00 MHz SGMIICLK_Q0_P SGMIICLK_Q0_N SGMIICLK_Q0_C_P SGMIICLK_Q0_C_N SGMIICLK_XTAL_IN GND_SGMIICLK GND OE 2 1 3 4 Table 1 18 Ethernet PHY Connections FPGA Pin U1 Schematic Net Name M88E1111 U37 Pin Number Pin Name J21 PHY_MDIO M1 MDIO R23 PHY_MDC L3 MDC N30 PHY_INT L1 INT_B L20 PHY_RESET K3 RESET_B R30 PHY_CRS B5 CRS W19 PHY_COL B6 COL U27 PHY_RXCLK C1 RXCLK V26...

Page 39: ...e FPGA fabric The FPGA supports the USB to UART bridge using four signal pins Transmit TX Receive RX Request to Send RTS and Clear to Send CTS Silicon Labs provides royalty free Virtual COM Port VCP drivers for the host computer These drivers permit the CP2103GM USB to UART bridge to appear as a COM port to communications application software for example TeraTerm or HyperTerm that runs on the host...

Page 40: ... following HDMI device interfaces 18 data lines Independent VSYNC HSYNC Single ended input CLK Interrupt Out Pin to FPGA I2 C SPDIF Table 1 19 USB J6 Mini B Receptacle Pin Assignments and Signal Definitions USB Receptacle Pins J6 Receptacle Pin Name Schematic Net Name Description U12 Pin CP2103GM U12 Pin Name CP2103GM 1 VBUS USB_VBUS 5V from host system U12 CP2103 power 7 8 REGIN VBUS 2 D_N USB_D_...

Page 41: ...0 2 98 56 55 50 46 45 38 21 24 25 34 41 29 99 100 23 18 20 22 27 31 37 75 47 26 76 77 49 19 1 30 U65 ADV7511 HDMI_D10 VADJ HDMI_HEAC_C_N HDMI_AVDD HDMI_PLVDD HDMI_PLVDD 2 1 X5R 25V 0 1UF C592 HDMI_CLK HDMI_HSYNC HDMI_VSYNC HDMI_INT 1 1 1 10W 2 43K R389 R435 2 43K 1 10W 1 IIC_SCL_HDMI 1 2 3 4 U72 12 00000 MHZ SIT8102 50PPM VCC2V5 IIC_SDA_HDMI HDMI_DVDD HDMI_DE R388 2 43K 1 10W 1 HDMI_SPDIF HDMI_AVD...

Page 42: ...I_D3 85 D11 F25 HDMI_D4 84 D12 E25 HDMI_D5 83 D13 E24 HDMI_D6 82 D14 D24 HDMI_D7 81 D15 F26 HDMI_D8 80 D16 E26 HDMI_D9 78 D17 G23 HDMI_D10 74 D18 G24 HDMI_D11 73 D19 J19 HDMI_D12 72 D20 H19 HDMI_D13 71 D21 L17 HDMI_D14 70 D22 L18 HDMI_D15 69 D23 K19 HDMI_D16 68 D24 K20 HDMI_D17 67 D25 H17 HDMI_DE 97 DE J17 HDMI_SPDIF 10 SPDIF K18 HDMI_CLK 79 CLK H20 HDMI_VSYNC 2 VSYNC J18 HDMI_HSYNC 98 HSYNC AH24 ...

Page 43: ... connected to the FPGA s 1 5V HP bank 33 through a Texas Instruments TXS0108E 8 bit bidirectional voltage level translator U10 Figure 1 21 shows the LCD interface circuit 42 HDMI_D2_N 3 33 HDMI_CLK_P 10 32 HDMI_CLK_N 12 54 HDMI_DDCSDA 16 53 HDMI_DDCSCL 15 52 HDMI_HEAC_P 14 51 HDMI_HEAC_N 19 48 HDMI_CRC 13 Table 1 22 ADV7511 to HDMI Connector Connections Cont d ADV7511 U65 Schematic Net Name HDMI C...

Page 44: ...RS LCD_E NC NC LCD_DB5 LCD_DB7 9 8 7 6 5 4 3 2 10 1 12 14 11 13 LCD_VEE GND VCCB B1 B2 B3 B4 B6 B7 GND A3 A8 OE A4 A5 A7 A6 B5 A1 A2 B8 VCCA 19 20 18 17 16 14 13 11 4 9 10 5 6 8 7 15 1 3 12 2 U10 VCC1V5_FPGA LCD_E_LS LCD_RW_LS LCD_DB4_LS LCD_DB5_LS LCD_DB6_LS LCD_DB7_LS LCD_RS_LS NC LCD_RS LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_RW LCD_E NC TXS0108E 8 Bit Bidirectional Voltage Level Translator J31 GND...

Page 45: ...ce The KC705 board I2C bus topology is shown in Figure 1 23 User applications that communicate with devices on one of the downstream I2 C buses must first set up a path to the desired bus through the U49 bus switch at I2 C address 0x74 0b01110100 Table 1 23 FPGA to LCD Header Connections FPGA Pin U1 Schematic Net Name LCD Header Pin J31 AA13 LCD_DB4_LS 4 AA10 LCD_DB5_LS 3 AA11 LCD_DB6_LS 2 Y10 LCD...

Page 46: ...XXXX00 FMC_LPC_IIC_SDA SCL 2 0bXXXXX00 EEPROM_IIC_SDA SCL 3 0b1010100 SFP_IIC_SDA SCL 4 0b1010000 IIC_SDA SCL_HDMI 5 0b0111001 IIC_SDA SCL_DDR3 6 0b1010000 0b0011000 Si5324_SDA SCL 7 0b1101000 Table 1 25 Status LEDs Reference Designator Signal Name Color Description DS14 PWRCTL1_VCC4A_PG GREEN FMC Power Good DS20 FPGA_DONE GREEN FPGA Configured Successfully DS21 FPGA_INIT_B GREEN RED GREEN FPGA In...

Page 47: ...llout 22 GPIO_LED_ 7 0 DS27 DS26 DS25 DS3 DS10 DS1 DS4 Five user pushbuttons and reset switch callout 23 GPIO_SW_ NESWC SW2 SW3 SW4 SW6 SW5 CPU_RESET SW7 4 position user DIP Switch callout 24 GPIO_DIP_SW 3 0 SW11 X Ref Target Figure 1 24 Figure 1 24 Ethernet PHY Status LEDs Direction Indicator Link Rate Mbps TX 100 RX Half Duplex 10 1000 RJ45 Ethernet Jack UG810_c1_103_031412 Table 1 26 Ethernet P...

Page 48: ... Character Display callout 19 If the display is unmounted connector J31 pins are available as 7 independent 5V GPIOs User GPIO LEDs Figure 1 2 callout 34 Figure 1 25 shows the user LED circuits X Ref Target Figure 1 25 Figure 1 25 User LEDs UG810_c1_23_072511 R93 49 9Ω 1 DS4 R94 49 9Ω 1 DS1 R95 49 9Ω 1 DS10 R96 49 9Ω 1 DS2 R97 49 9Ω 1 DS3 R440 49 9Ω 1 DS25 R441 49 9Ω 1 DS26 R442 49 9Ω 1 GND DS27 G...

Page 49: ...n circuit X Ref Target Figure 1 26 Figure 1 26 User Pushbuttons UG810_c1_24_072511 VADJ GPIO SW C R13 4 7kΩ 0 1 W 5 GND 4 3 2 1 SW5 VCC1V5 GPIO SW N R13 4 7kΩ 0 1 W 5 GND 4 3 2 1 SW2 VCC1V5 GPIO SW S R12 4 7kΩ 0 1 W 5 GND 4 3 2 1 SW4 VCC1V5 GPIO SW W R14 4 7kΩ 0 1 W 5 GND 4 3 2 1 SW6 VCC1V5 GPIO SW E R11 4 7kΩ 0 1 W 5 GND 4 3 2 1 SW3 X Ref Target Figure 1 27 Figure 1 27 CPU Reset Pushbutton UG810_...

Page 50: ...rget Figure 1 28 Figure 1 28 GPIO DIP Switch SDA04H1SBD SW11 VADJ GPIO_DIP_SW3 GPIO_DIP_SW2 GPIO_DIP_SW1 GPIO_DIP_SW0 R25 4 7kΩ 0 1 W 5 R24 4 7kΩ 0 1 W 5 R23 4 7kΩ 0 1 W 5 R22 4 7kΩ 0 1 W 5 1 2 3 4 8 7 6 5 GND X Ref Target Figure 1 29 Figure 1 29 Rotary Switch SW8 VCC1V8 GND GND SW8 R31 4 7K 1 10W 5 R30 4 7K 1 10W 5 R32 4 7K 1 10W 5 Edge Drive Jog Encoder EVQ WK4001 GND ROTARY INCB ROTARY PUSH 6 5...

Page 51: ...d J14 Table 1 27 GPIO Connections to FPGA U1 FPGA Pin U1 Schematic Net Name GPIO Pin Indicator LEDs Active High AB8 GPIO_LED_0 DS4 2 AA8 GPIO_LED_1 DS1 2 AC9 GPIO_LED_2 DS10 2 AB9 GPIO_LED_3 DS2 2 AE26 GPIO_LED_4 DS3 2 G19 GPIO_LED_5 DS25 2 E18 GPIO_LED_6 DS26 2 F16 GPIO_LED_7 DS27 2 Directional Push Button Switches AA12 GPIO_SW_N SW2 1 AG5 GPIO_SW_E SW3 1 AB12 GPIO_SW_S SW4 1 GND UG885_c1_201_032...

Page 52: ... KC705 board power is on See Power Management for details on the onboard power system Caution Do NOT plug a PC ATX power supply 6 pin connector into J49 on the KC705 board The ATX 6 pin connector has a different pinout than J49 Connecting an ATX 6 pin connector into J49 will damage the KC705 board and void the board warranty AC6 GPIO_SW_W SW6 1 G12 GPIO_SW_C SW5 1 AB7 CPU_RESET SW7 1 4 Pole DIP Sw...

Page 53: ... action initiates an FPGA reconfiguration The FPGA_PROG_B signal is connected to FPGA U1 pin K10 See UG470 7 Series FPGAs Configuration User Guide for further details on configuring the 7 series FPGAs Figure 1 33 shows SW14 X Ref Target Figure 1 31 Figure 1 31 Power On Off Switch SW15 X Ref Target Figure 1 32 Figure 1 32 ATX Power Supply Adapter Cable VCC12_P_IN VCC12_P R369 1kΩ 1 INPUT_GND 1 2 3 ...

Page 54: ...FPGA Mezzanine Card FMC specification by providing subset implementations of a high pin count HPC connector at J22 and a low pin count LPC connector at J2 Both connectors use the same 10 x 40 form factor except the HPC version is fully populated with 400 pins and the LPC version is partially populated with 160 pins Both connectors are keyed so that a the mezzanine card faces away from the KC705 bo...

Page 55: ...is connectivity 58 differential user defined pairs 34 LA pairs LA00 LA33 24 HA pairs HA00 HA23 4 GTX transceivers 1 GTX clock 2 differential clocks 159 ground and 15 power connections The HPC signals are distributed across GTX Quads 116 117 and 118 Each of these Quads have their VCCO voltage connected to VADJ Note The KC705 board VADJ voltage for the J22 and J2 connectors is determined by the FMC ...

Page 56: ... D9 FMC_HPC_LA01_CC_N C26 C11 FMC_HPC_LA06_N G30 D11 FMC_HPC_LA05_P G29 C14 FMC_HPC_LA10_P D29 D12 FMC_HPC_LA05_N F30 C15 FMC_HPC_LA10_N C30 D14 FMC_HPC_LA09_P B30 C18 FMC_HPC_LA14_P B28 D15 FMC_HPC_LA09_N A30 C19 FMC_HPC_LA14_N A28 D17 FMC_HPC_LA13_P A25 C22 FMC_HPC_LA18_CC_P F21 D18 FMC_HPC_LA13_N A26 C23 FMC_HPC_LA18_CC_N E21 D20 FMC_HPC_LA17_CC_P F20 C26 FMC_HPC_LA27_P C19 D21 FMC_HPC_LA17_CC_...

Page 57: ...MC_HPC_HA13_P L16 F11 FMC_HPC_HA08_N E15 E13 FMC_HPC_HA13_N K16 F13 FMC_HPC_HA12_P C15 E15 FMC_HPC_HA16_P L15 F14 FMC_HPC_HA12_N B15 E16 FMC_HPC_HA16_N K15 F16 FMC_HPC_HA15_P H15 E18 FMC_HPC_HA20_P K13 F17 FMC_HPC_HA15_N G15 E19 FMC_HPC_HA20_N J13 F19 FMC_HPC_HA19_P H11 E21 NC F20 FMC_HPC_HA19_N H12 E22 NC F22 NC E24 NC F23 NC E25 NC F25 NC E27 NC F26 NC E28 NC F28 NC E30 NC F29 NC E31 NC F31 NC E...

Page 58: ...15_P C24 G22 FMC_HPC_LA20_N D19 H20 FMC_HPC_LA15_N B24 G24 FMC_HPC_LA22_P C20 H22 FMC_HPC_LA19_P G18 G25 FMC_HPC_LA22_N B20 H23 FMC_HPC_LA19_N F18 G27 FMC_HPC_LA25_P G17 H25 FMC_HPC_LA21_P A20 G28 FMC_HPC_LA25_N F17 H26 FMC_HPC_LA21_N A21 G30 FMC_HPC_LA29_P C17 H28 FMC_HPC_LA24_P A16 G31 FMC_HPC_LA29_N B17 H29 FMC_HPC_LA24_N A17 G33 FMC_HPC_LA31_P G22 H31 FMC_HPC_LA28_P D16 G34 FMC_HPC_LA31_N F22 ...

Page 59: ...ial user defined pairs 34 LA pairs LA00 LA33 J12 FMC_HPC_HA11_P B13 K11 FMC_HPC_HA06_N C14 J13 FMC_HPC_HA11_N A13 K13 FMC_HPC_HA10_P A11 J15 FMC_HPC_HA14_P J16 K14 FMC_HPC_HA10_N A12 J16 FMC_HPC_HA14_N H16 K16 FMC_HPC_HA17_CC_P G13 J18 FMC_HPC_HA18_P K14 K17 FMC_HPC_HA17_CC_N F13 J19 FMC_HPC_HA18_N J14 K19 FMC_HPC_HA21_P J11 J21 FMC_HPC_HA22_P L11 K20 FMC_HPC_HA21_N J12 J22 FMC_HPC_HA22_N K11 K22 ...

Page 60: ...22 C14 FMC_LPC_LA10_P AJ24 D12 FMC_LPC_LA05_N AH22 C15 FMC_LPC_LA10_N AK25 D14 FMC_LPC_LA09_P AK23 C18 FMC_LPC_LA14_P AD21 D15 FMC_LPC_LA09_N AK24 C19 FMC_LPC_LA14_N AK21 D17 FMC_LPC_LA13_P AB24 C22 FMC_LPC_LA18_CC_P AD27 D18 FMC_LPC_LA13_N AC25 C23 FMC_LPC_LA18_CC_N AD28 D20 FMC_LPC_LA17_CC_P AB27 C26 FMC_LPC_LA27_P AJ28 D21 FMC_LPC_LA17_CC_N AC27 C27 FMC_LPC_LA27_N AJ29 D23 FMC_LPC_LA23_P AH26 C...

Page 61: ...LA04_P AH21 G13 FMC_LPC_LA08_N AJ23 H11 FMC_LPC_LA04_N AJ21 G15 FMC_LPC_LA12_P AA20 H13 FMC_LPC_LA07_P AG25 G16 FMC_LPC_LA12_N AB20 H14 FMC_LPC_LA07_N AH25 G18 FMC_LPC_LA16_P AC22 H16 FMC_LPC_LA11_P AE25 G19 FMC_LPC_LA16_N AD22 H17 FMC_LPC_LA11_N AF25 G21 FMC_LPC_LA20_P AF26 H19 FMC_LPC_LA15_P AC24 G22 FMC_LPC_LA20_N AF27 H20 FMC_LPC_LA15_N AD24 G24 FMC_LPC_LA22_P AJ27 H22 FMC_LPC_LA19_P AJ26 G25 ...

Page 62: ...INT XADC VCC VCC5V0 VCCAUX_IO VCC_SPI VCCBRAM MGTVCCAUX Power Controller 2 Aux U56 Address 53 Switching Regulator 2 5V at 10A U104 Switching Regulator 1 5V at 10A Switching Regulator 1 2V at 10A U105 Switching Regulator 1 0V at 10A Linear Regulator 5 0V at 2A U71 Linear Regulator 1 7V 2 0V at 300 mA U39 Linear Regulator 2 8V at 300 MA U62 Switching Regulator 1 8V at 10A U99 Power Controller 3 U89 ...

Page 63: ...3 40 PTD08D021W VOUT A U104 Adjustable switching regulator dual 10A 0 6Vto 3 6V VCC2V5_FPGA 2 50V 41 PTD08D021W VOUT B Adjustable switching regulator dual 10A 0 6Vto 3 6V VCC1V5_FPGA 1 50V 41 PTD08D021W VOUT A U105 Adjustable switching regulator dual 10A 0 6Vto 3 6V MGTAVCC 1 00V 42 PTD08D021W VOUT B Adjustable switching regulator dual 10A 0 6Vto 3 6V MGTAVTT 1 20V 42 UCD9248PFC 3 U89 PMBus Contro...

Page 64: ...ing other than the default setting of 2 5V Once the new FMC_VADJ voltage level has been programmed into TI controller U55 the FMC_VADJ_ON_B signal can be driven low by the user logic and the FMC_VADJ rail will come up at the new FMC_VADJ voltage level Installing a jumper at J65 after a KC705 board powers up in this mode will turn on the FMC_VADJ rail For access to Texas Instruments fusion tools do...

Page 65: ... are relative to when the board power on off slide switch SW15 is turned on and off Table 1 31 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at Address 52 U55 Table 1 32 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at Address 53 U56 Table 1 31 Power Rail Specifications for UCD9248 PMBus...

Page 66: ...1 The values defined in these columns are the voltage current and temperature thresholds that will cause the regulator to shut down if the value is exceeded Table 1 32 Power Rail Specifications for UCD9248 PMBus controller at Address 53 Cont d Shutdown Threshold 1 Rail Number Rail Name Schematic Rail Name Nominal V OUT V PG On Threshold V PG Off Threshold V On Delay ms Rise Time ms Off Delay ms Fa...

Page 67: ... 0 and Channel 8 is supported A user provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines Figure 1 38 shows the XADC header connections X Ref Target Figure 1 37 Figure 1 37 Header XADC_VREF Voltage Source Options FPGA U1 VAUX0N VAUX0P VAUX8N VAUX8P VREF 1 25V VREFN VCCADC GNDA...

Page 68: ...g input channel for the XADC XADC_VAUX0P N 3 6 Auxiliary analog input channel 0 Also supports use as IO inputs when anti alias capacitor is not present XADC_VAUX8N P 7 8 Auxiliary analog input channel 8 Also supports use as IO inputs when anti alias capacitor is not present DXP DXN 9 12 Access to thermal diode XADC_AGND 4 5 10 Analog ground reference XADC_VREF 11 1 25V reference from the board XAD...

Page 69: ...iguring the FPGA DIP switch SW13 also provides the upper two address bits for the Linear BPI Flash and can be used to select one of multiple stored configuration bitstreams Figure 1 40 shows the connectivity between the onboard non volatile Flash devices used for configuration and the FPGA To obtain the fastest configuration speed an external 66 MHz oscillator is wired to the EMCCLK pin of the FPG...

Page 70: ...C705 Board Configuration Circuit UG810_c1_33_031612 RST_B CLK WE_B OE_B ADV_B D 15 00 A 27 01 U58 P30 1Gb Flash Memory D Q HOLD_B W_B C S B U7 N25Q128A13BSF 40F QUAD SPI TCK TMS TDI TDO Bank 0 CCLK INIT_B VBATT M 2 0 DONE PROG_B U1 FPGA SW14 Bank 15 Bank 14 FWE_B FOE_B ADV_B RS1 RS0 A 26 25 A 24 16 A 15 00 D 15 00 FCS_B EMCCLK CSO_B POUC_B GND VCCAUXIO 2 0V 5 kΩ GND 27 4 Ω GND R405 1 kΩ 300 Ω D11 ...

Page 71: ...1 2 page 8 Item 29 for location of SW13 Default settings are shown in Figure A 2 and details are listed in Table A 2 X Ref Target Figure A 1 Figure A 1 SW11 Default Settings Table A 1 SW11 Default Switch Settings Position Function Default 1 GPIO_DIP_SW3 Off 2 GPIO_DIP_SW2 Off 3 GPIO_DIP_SW1 Off 4 GPIO_DIP_SW0 Off UG810_aB_01_010512 GPIO DIP SW 1 SW11 OFF Position 0 ON Position 1 2 3 4 X Ref Target...

Page 72: ...rs listed in Table A 3 Table A 2 SW13 Default Switch Settings Position Function Default 1 FLASH_A25 A25 Off 2 FLASH_A24 A24 Off 3 FPGA_M2 M0 Off 4 FPGA_M1 M1 On 5 FPGA_M0 M3 Off Table A 3 Default Jumper Settings Jumper Default Jumper Position J32 Pin 5 to pin 6 J28 Pin 2 to pin 3 J29 Pin 1 to pin 2 J30 Pin 1 to pin 2 J5 None J3 Pin 1 to pin 2 J43 Pin 1 to pin 2 J42 None J47 Pin 1 to pin 2 J48 Pin ...

Page 73: ... GND DP5_M2C_P DP5_M2C_N GND GND DP1_C2M_P DP1_C2M_N GND GND DP2_C2M_P DP2_C2M_N GND GND DP3_C2M_P DP3_C2M_N GND GND DP4_C2M_P DP4_C2M_N GND GND DP5_C2M_P DP5_C2M_N GND RES1 GND GND DP9_M2C_P DP9_M2C_N GND GND DP8_M2C_P DP8_M2C_N GND GND DP7_M2C_P DP7_M2C_N GND GND DP6_M2C_P DP6_M2C_N GND GND GBTCLK1_M2C_P GBTCLK1_M2C_N GND GND DP9_C2M_P DP9_C2M_N GND GND DP8_C2M_P DP8_C2M_N GND GND DP7_C2M_P DP7_...

Page 74: ...A13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND UG810_aC_02_031812 K J H ...

Page 75: ...DIO_CD_DAT3_LS LOC AC21 IOSTANDARD LVCMOS25 Bank 12 VCCO VADJ_FPGA IO_L5N_T0_12 NET FMC_LPC_LA12_P LOC AA20 IOSTANDARD LVCMOS25 Bank 12 VCCO VADJ_FPGA IO_L6P_T0_12 NET FMC_LPC_LA12_N LOC AB20 IOSTANDARD LVCMOS25 Bank 12 VCCO VADJ_FPGA IO_L6N_T0_VREF_12 NET FMC_LPC_LA13_P LOC AB24 IOSTANDARD LVCMOS25 Bank 12 VCCO VADJ_FPGA IO_L7P_T1_12 NET FMC_LPC_LA13_N LOC AC25 IOSTANDARD LVCMOS25 Bank 12 VCCO VA...

Page 76: ...LPC_LA17_CC_N LOC AC27 IOSTANDARD LVCMOS25 Bank 13 VCCO VADJ_FPGA IO_L12N_T1_MRCC_13 NET FMC_LPC_CLK1_M2C_P LOC AG29 IOSTANDARD LVCMOS25 Bank 13 VCCO VADJ_FPGA IO_L13P_T2_MRCC_13 NET FMC_LPC_CLK1_M2C_N LOC AH29 IOSTANDARD LVCMOS25 Bank 13 VCCO VADJ_FPGA IO_L13N_T2_MRCC_13 NET FMC_LPC_LA29_P LOC AE28 IOSTANDARD LVCMOS25 Bank 13 VCCO VADJ_FPGA IO_L14P_T2_SRCC_13 NET FMC_LPC_LA29_N LOC AF28 IOSTANDAR...

Page 77: ...TS LOC K23 IOSTANDARD LVCMOS25 Bank 15 VCCO VCC2V5_FPGA IO_L3P_T0_DQS_AD1P_15 NET USB_RX LOC K24 IOSTANDARD LVCMOS25 Bank 15 VCCO VCC2V5_FPGA IO_L3N_T0_DQS_AD1N_15 NET IIC_SDA_MAIN LOC L21 IOSTANDARD LVCMOS25 Bank 15 VCCO VCC2V5_FPGA IO_L4P_T0_AD9P_15 NET IIC_SCL_MAIN LOC K21 IOSTANDARD LVCMOS25 Bank 15 VCCO VCC2V5_FPGA IO_L4N_T0_AD9N_15 NET PHY_MDIO LOC J21 IOSTANDARD LVCMOS25 Bank 15 VCCO VCC2V5...

Page 78: ..._L18P_T2_16 NET FMC_HPC_LA08_N LOC E30 IOSTANDARD LVCMOS25 Bank 16 VCCO VADJ_FPGA IO_L18N_T2_16 NET FMC_HPC_LA02_P LOC H24 IOSTANDARD LVCMOS25 Bank 16 VCCO VADJ_FPGA IO_L19P_T3_16 NET FMC_HPC_LA02_N LOC H25 IOSTANDARD LVCMOS25 Bank 16 VCCO VADJ_FPGA IO_L19N_T3_VREF_16 NET FMC_HPC_LA04_P LOC G28 IOSTANDARD LVCMOS25 Bank 16 VCCO VADJ_FPGA IO_L20P_T3_16 NET FMC_HPC_LA04_N LOC F28 IOSTANDARD LVCMOS25 ...

Page 79: ...NET FMC_HPC_HA14_P LOC J16 IOSTANDARD LVCMOS25 Bank 18 VCCO VADJ_FPGA IO_L9P_T1_DQS_18 NET FMC_HPC_HA14_N LOC H16 IOSTANDARD LVCMOS25 Bank 18 VCCO VADJ_FPGA IO_L9N_T1_DQS_18 NET FMC_HPC_HA19_P LOC H11 IOSTANDARD LVCMOS25 Bank 18 VCCO VADJ_FPGA IO_L10P_T1_18 NET FMC_HPC_HA19_N LOC H12 IOSTANDARD LVCMOS25 Bank 18 VCCO VADJ_FPGA IO_L10N_T1_18 NET FMC_HPC_HA01_CC_P LOC H14 IOSTANDARD LVCMOS25 Bank 18 ...

Page 80: ...T GPIO_SW_N LOC AA12 IOSTANDARD LVCMOS15 Bank 33 VCCO VCC1V5_FPGA IO_L1P_T0_33 NET GPIO_SW_S LOC AB12 IOSTANDARD LVCMOS15 Bank 33 VCCO VCC1V5_FPGA IO_L1N_T0_33 NET GPIO_LED_1_LS LOC AA8 IOSTANDARD LVCMOS15 Bank 33 VCCO VCC1V5_FPGA IO_L2P_T0_33 NET GPIO_LED_0_LS LOC AB8 IOSTANDARD LVCMOS15 Bank 33 VCCO VCC1V5_FPGA IO_L2N_T0_33 NET GPIO_LED_3_LS LOC AB9 IOSTANDARD LVCMOS15 Bank 33 VCCO VCC1V5_FPGA I...

Page 81: ...1V5_FPGA IO_L13N_T2_MRCC_34 NET DDR3_D41 LOC AH6 IOSTANDARD SSTL15 Bank 34 VCCO VCC1V5_FPGA IO_L14P_T2_SRCC_34 NET DDR3_D40 LOC AH5 IOSTANDARD SSTL15 Bank 34 VCCO VCC1V5_FPGA IO_L14N_T2_SRCC_34 NET DDR3_DQS5_P LOC AG2 IOSTANDARD DIFF_SSTL15 Bank 34 VCCO VCC1V5_FPGA IO_L15P_T2_DQS_34 NET DDR3_DQS5_N LOC AH1 IOSTANDARD DIFF_SSTL15 Bank 34 VCCO VCC1V5_FPGA IO_L15N_T2_DQS_34 NET DDR3_D43 LOC AH2 IOSTA...

Page 82: ...1N_117 NET SMA_MGT_REFCLK_P LOC J8 Bank 117 MGTREFCLK1P_117 NET SGMII_TX_P LOC J4 Bank 117 MGTXTXP1_117 NET SGMII_RX_P LOC H6 Bank 117 MGTXRXP1_117 NET SGMII_TX_N LOC J3 Bank 117 MGTXTXN1_117 NET SGMII_RX_N LOC H5 Bank 117 MGTXRXN1_117 NET SMA_MGT_TX_P LOC K2 Bank 117 MGTXTXP0_117 NET SMA_MGT_RX_P LOC K6 Bank 117 MGTXRXP0_117 NET SMA_MGT_TX_N LOC K1 Bank 117 MGTXTXN0_117 NET SMA_MGT_RX_N LOC K5 Ba...

Page 83: ...ower cord from the PC 3 Open the PC chassis following the instructions provided with the PC 4 Select a vacant PCIe expansion slot and remove the expansion cover at the back of the chassis by removing the screws on the top and bottom of the cover 5 Plug the KC705 board into the PCIe connector at this slot 6 Install the top mounting bracket screw into the PC expansion cover retainer bracket to secur...

Page 84: ...Appendix D Board Setup 84 www xilinx com KC705 Evaluation Board UG810 v1 3 May 10 2013 8 Slide the KC705 board power switch SW12 to the ON position The PC can now be powered on ...

Page 85: ...fications Dimensions Height 5 5 in 14 0 cm Length 10 5 in 26 7 cm Note The KC705 board height exceeds the standard 4 376 in 11 15 cm height of a PCI Express card Environmental Temperature Operating 0 C to 45 C Storage 25 C to 60 C Humidity 10 to 90 non condensing Operating Voltage 12 VDC ...

Page 86: ...Appendix E Board Specifications 86 www xilinx com KC705 Evaluation Board UG810 v1 3 May 10 2013 ...

Page 87: ...ces software tools and intellectual property at all stages of the design cycle Topics include design assistance advisories and troubleshooting tips Further Resources The most up to date information related to the KC705 board and its documentation is available on the following websites The KC705 Evaluation Kit Product Page www xilinx com kc705 The KC705 Evaluation Kit Master Answer Record http www ...

Page 88: ...grated Device Technology www idt com ICS844021 01 4 Marvell Semiconductor http www marvell com and www marvell com transceivers alaska gbe 88E1111 5 Micron Semiconductor http www micron com Numonyx PC28F00AP30TF N25Q128A13BSF40F and MT8JTF12864HZ 1G6G1 6 Samtec www samtec com SEAF series connectors 7 Si Time http www sitime com SiT9102 8 Silicon Labs http www silabs com Si570 Si5324C 9 Texas Instr...

Page 89: ...larations of conformity xtp251 zip Directives 2006 95 EC Low Voltage Directive LVD 2004 108 EC Electromagnetic Compatibility EMC Directive Standards EN standards are maintained by the European Committee for Electrotechnical Standardization CENELEC IEC standards are maintained by the International Electrotechnical Commission IEC Electromagnetic Compatibility EN 55022 2010 Information Technology Equ...

Page 90: ...is product complies with Directive 2002 96 EC on waste electrical and electronic equipment WEEE The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste This product complies with Directive 2002 95 EC on the restriction of hazardous substances RoHS in electrical and electronic equipment This product complies with CE Direct...

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