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Spartan-3A DSP FPGA Family: DC and Switching Characteristics

DS610 (v3.0) October 4, 2010

www.xilinx.com

Product Specification

Configuration and JTAG Timing

General Configuration Power-On/Reconfigure Timing

X-Ref Target - Figure 10

Figure 10:

Waveforms for Power-On and the Beginning of Configuration

Table 45:

Power-On Timing and the Beginning of Configuration

Symbol

Description

Device

All Speed Grades

Units

Min

Max

POR

(2)

The time from the application of V

CCINT

, V

CCAUX

, and V

CCO

Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin

All

–

PROG

The width of the low-going pulse on the PROG_B pin

All

0.5

–

µs

(2)

The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin

All

–

INIT

Minimum Low pulse width on INIT_B output

All

300

–

ICCK

(3)

The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin

All

0.5

µs

Notes:

The numbers in this table are based on the operating conditions set forth in

Table 7

. This means power must be applied to all V

CCINT

, V

CCO

and V

CCAUX

lines.

Power-on reset and the clearing of configuration memory occurs during this period.

This specification applies only to the Master Serial, SPI, and BPI modes.

For details on configuration, see

UG332

Spartan-3 Generation Configuration User Guide

CCINT

(Supply)

CCAUX

CCO

Bank 2

PROG_B

(Output)

(Open-Drain)

(Input)

INIT_B

CCLK

DS529-3_01_052708

1.2V

2.5V

ICCK

PROG

POR

1.0V

2.0V

3.3V

2.5V

3.3V

Notes:

The V

CCINT

, V

CCAUX

, and V

CCO

supplies can be applied in any order.

The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.

The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).

Summary of Contents for DS610

Page 1: ...ckage Drawings Powering FPGAs Power Management UG332 Spartan 3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior Bitstream Sizes Detailed Descriptions by Mode...

Page 2: ...multiply accumulate MAC operation Integrated adder for complex multiply or multiply add operation Integrated 18 bit pre adder Optional cascaded Multiply or MAC Hierarchical SelectRAM memory architectu...

Page 3: ...tiplying dividing and phase shifting clock signals These elements are organized as shown in Figure 1 A dual ring of staggered IOBs surrounds a regular array of CLBs The XC3SD1800A has four columns of...

Page 4: ...d Device DNA identifier useful for tracking purposes anti cloning designs or IP protection I O Capabilities The Spartan 3A DSP FPGA SelectIO interface supports many popular single ended and differenti...

Page 5: ...de Package Type Number of Pins Power Temperature Range TJ XC3SD1800A 4 Standard Performance CS484 CSG484 484 ball Chip Scale Ball Grid Array CSBGA C Commercial 0 C to 85 C XC3SD3400A 5 High Performanc...

Page 6: ...PROPERTY OR ENVIRONMENTAL DAMAGE INDIVIDUALLY AND COLLECTIVELY CRITICAL APPLICATIONS FURTHERMORE XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHI...

Page 7: ...Platform Flash PROM Master SPI Mode using Commodity SPI Serial Flash PROM Master BPI Mode using Commodity Parallel NOR Flash PROM Slave Parallel SelectMAP using a Processor Slave Serial using a Proces...

Page 8: ...SONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE INDIVIDUALLY AND COLLECTIVELY CRITICAL APPLICATIONS FURTHERMORE XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AF...

Page 9: ...umbers for both commercial and industrial grades Absolute Maximum Ratings Stresses beyond those listed under Table 3 Absolute Maximum Ratings may cause permanent damage to the device These are stress...

Page 10: ...point Table 5 Supply Voltage Ramp Rate Symbol Description Min Max Units VCCINTR Ramp rate from GND to valid VCCINT supply level 0 2 100 ms VCCAUXR Ramp rate from GND to valid VCCAUX supply level 0 2...

Page 11: ...0 5 4 10 V TIN Input signal transition time 5 500 ns Notes 1 This VCCO range spans the lowest and highest operating voltages for all supported I O standards Table 10 lists the recommended VCCO range...

Page 12: ...4 74 0 k VCCO 1 14V to 1 26V 15 3 41 1 119 4 k IRPD 3 Current through pull down resistor at User I O Dual Purpose Input only and Dedicated pins VIN VCCO VCCAUX 3 0V to 3 6V 167 346 659 A VCCAUX 2 25V...

Page 13: ...s are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with VCCINT 1 26V VCCO 3 6V and VCCAUX 3 6V The FPGA is programmed with a blank conf...

Page 14: ...5 1 7 VREF 0 2 VREF 0 2 SSTL3_II 3 0 3 3 3 6 1 3 1 5 1 7 VREF 0 2 VREF 0 2 Notes 1 Descriptions of the symbols used in this table are as follows VCCO the supply voltage for output drivers VREF the ref...

Page 15: ...81 SSTL3_I 8 8 VTT 0 6 VTT 0 6 SSTL3_II 5 16 16 VTT 0 8 VTT 0 8 Notes 1 The numbers in this table are based on the conditions set forth in Table 7 and Table 10 2 Descriptions of the symbols used in th...

Page 16: ...DIFF_HSTL_I 1 4 1 5 1 6 100 0 68 0 9 DIFF_HSTL_III 1 4 1 5 1 6 100 0 9 DIFF_SSTL18_I 1 7 1 8 1 9 100 0 7 1 1 DIFF_SSTL18_II 8 1 7 1 8 1 9 100 0 7 1 1 DIFF_SSTL2_I 2 3 2 5 2 7 100 1 0 1 5 DIFF_SSTL2_I...

Page 17: ...475 VTT 0 475 DIFF_SSTL18_II VTT 0 603 VTT 0 603 DIFF_SSTL2_I VTT 0 61 VTT 0 61 DIFF_SSTL2_II VTT 0 81 VTT 0 81 DIFF_SSTL3_I VTT 0 6 VTT 0 6 DIFF_SSTL3_II VTT 0 8 VTT 0 8 Notes 1 The numbers in this t...

Page 18: ...Input only differential pairs or pairs not using DIFF_TERM Yes constraint Z0 50 Z0 50 b Differential pairs using DIFF_TERM Yes constraint DIFF_TERM No DIFF_TERM Yes LVDS_33 MINI_LVDS_33 RSDS_33 PPDS_...

Page 19: ...oward Production status rerun the latest Xilinx ISE software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates Production designs will r...

Page 20: ...F the time from the active transition on the Global Clock pin to data appearing at the Output pin The DCM is not in use LVCMOS25 2 12 mA output drive Fast slew rate without DCM XC3SD1800A 5 23 5 58 ns...

Page 21: ...4 XC3SD1800A 0 38 0 38 ns XC3SD3400A 0 26 0 26 ns TPHFD When writing to IFF the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin The DCM is...

Page 22: ...ns XC3SD3400A 1 51 1 88 ns TIOPICKD Time from the setup of data at the Input pin to the active transition at the ICLK input of the Input Flip Flop IFF The Input Delay is programmed LVCMOS25 2 1 XC3SD1...

Page 23: ...Table 7 and Table 10 2 This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input If this is true add the appropriate Input adjustment from Table...

Page 24: ...C3SD3400A 0 73 0 93 ns TIOPID The time it takes for data to travel from the Input pin to the I output with the input delay programmed LVCMOS25 2 1 XC3SD1800A 1 29 1 62 ns 2 1 67 2 08 ns 3 1 92 2 36 ns...

Page 25: ...39 3 86 ns 4 3 89 4 43 ns 5 3 83 4 39 ns 6 4 61 5 32 ns 7 5 40 6 24 ns 8 5 93 6 86 ns 1 XC3SD3400A 2 21 2 67 ns 2 2 71 3 25 ns 3 3 58 4 04 ns 4 4 15 4 62 ns 5 4 03 4 49 ns 6 4 57 5 31 ns 7 5 34 6 18...

Page 26: ...BLVDS_25 0 79 0 79 ns MINI_LVDS_25 0 78 0 78 ns MINI_LVDS_33 0 79 0 79 ns LVPECL_25 0 78 0 78 ns LVPECL_33 0 79 0 79 ns RSDS_25 0 79 0 79 ns RSDS_33 0 77 0 77 ns TMDS_33 0 79 0 79 ns PPDS_25 0 79 0 7...

Page 27: ...Output pin LVCMOS25 2 12 mA output drive Fast slew rate All 2 78 2 91 ns Set Reset Times TIOSRP Time from asserting the OFF s SR input to setting resetting data at the Output pin LVCMOS25 2 12 mA outp...

Page 28: ...Times TGTS Time from asserting the Global Three State GTS input on the STARTUP_SPARTAN3A primitive to when the Output pin enters the high impedance state LVCMOS25 12 mA output drive Fast slew rate All...

Page 29: ...0 59 0 59 ns 24 mA 0 60 0 60 ns QuietIO 2 mA 27 67 27 67 ns 4 mA 27 67 27 67 ns 6 mA 27 67 27 67 ns 8 mA 16 71 16 71 ns 12 mA 16 67 16 67 ns 16 mA 16 22 16 22 ns 24 mA 12 11 12 11 ns LVCMOS33 Slow 2 m...

Page 30: ...Adjustment Below Units Speed Grade 5 4 LVCMOS18 Slow 2 mA 4 48 4 48 ns 4 mA 3 69 3 69 ns 6 mA 2 91 2 91 ns 8 mA 1 99 1 99 ns 12 mA 1 57 1 57 ns 16 mA 1 19 1 19 ns Fast 2 mA 3 96 3 96 ns 4 mA 2 57 2 5...

Page 31: ...nputs Only LVPECL_33 RSDS_25 1 42 1 42 ns RSDS_33 0 58 0 58 ns TMDS_33 0 46 0 46 ns PPDS_25 1 07 1 07 ns PPDS_33 0 63 0 63 ns DIFF_HSTL_I_18 0 43 0 43 ns DIFF_HSTL_II_18 0 41 0 41 ns DIFF_HSTL_III_18...

Page 32: ...ample LVCMOS LVTTL then RT is set to 1M to indicate an open connection and VT is set to zero The same measurement point VM that was used at the Input is also used at the Output X Ref Target Figure 8 F...

Page 33: ...ICM 0 5 50 0 9 VICM DIFF_HSTL_II_18 VICM 0 5 VICM 0 5 50 0 9 VICM DIFF_HSTL_III_18 VICM 0 5 VICM 0 5 50 1 8 VICM DIFF_HSTL_I VICM 0 5 VICM 0 5 50 0 9 VICM DIFF_HSTL_III VICM 0 5 VICM 0 5 50 0 9 VICM D...

Page 34: ...n a large number of outputs simultaneously switch in the same direction The output drive transistors all conduct current to a common voltage rail Low to High transitions conduct to the VCCO rail High...

Page 35: ...0 60 4 41 41 6 29 29 8 22 22 12 13 13 16 11 11 24 9 9 Fast 2 10 10 4 6 6 6 5 5 8 3 3 12 3 3 16 3 3 24 2 2 QuietIO 2 80 80 4 48 48 6 36 36 8 27 27 12 16 16 16 13 13 24 12 12 LVCMOS33 Slow 2 76 76 4 46...

Page 36: ...CCAUX 3 3V Cont d Signal Standard IOSTANDARD Package Type CS484 FG676 Top Bottom Banks 0 2 Left Right Banks 1 3 LVCMOS18 Slow 2 64 64 4 34 34 6 22 22 8 18 18 12 13 16 10 Fast 2 18 18 4 9 9 6 7 7 8 4 4...

Page 37: ...STL3_I 4 5 DIFF_SSTL3_II 3 3 Notes 1 Not all I O standards are supported on all I O banks The left and right banks I O banks 1 and 3 support higher output drive current than the top and bottom banks I...

Page 38: ...ansition at the CLK input of the CLB 1 58 1 88 ns Hold Times TAH Time from the active transition at the CLK input to the point where data is last held at the F or G input 0 00 0 00 ns TCKDI Time from...

Page 39: ...s TDH Hold time of the BX and BY data inputs after the active transition at the CLK input of the distributed RAM 0 13 0 13 ns TAH TWH Hold time of the F G address inputs or the write enable input afte...

Page 40: ...bol Description Minimum Maximum Units Speed Grade 5 4 TGIO Global clock buffer BUFG BUFGMUX BUFGCE I input to O output delay 0 22 0 23 ns TGSI Global clock multiplexer BUFGMUX select S input setup to...

Page 41: ...he block RAM 0 64 0 75 ns TRCCK_REGCE Setup time for the CE input before the active transition at the CLK input of the block RAM 0 34 0 40 ns TRCCK_RST Setup time for the RST input before the active t...

Page 42: ...0 06 ns Setup Times of Data Pins to the Pipeline Register Clock TDSPDCK_AM A input to M register CLK Yes 3 30 3 79 ns TDSPDCK_BM B input to M register CLK Yes Yes 4 33 4 97 ns No Yes 3 30 3 79 ns TDSP...

Page 43: ...tput Yes 3 37 3 87 ns TDSPCKO_PD CLK DREG to P output Yes Yes Yes 7 33 8 42 ns Combinatorial Delays from Input Pins to Output Pins TDSPDO_AP TDSPDO_BP A or B input to P output No Yes 2 78 3 19 ns Yes...

Page 44: ...ue is zero Spread Spectrum DCMs accept typical spread spectrum clocks as long as they meet the input requirements The DLL will track the frequency changes created by the spread spectrum clock to drive...

Page 45: ...CLK2X and CLK2X180 outputs 0 5 of CLKIN period 100 0 5 of CLKIN period 100 ps CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing integer division 150 150 ps CLKOUT_PER_JITT_DV2 Per...

Page 46: ...size is 23 ps Table 38 Recommended Operating Conditions for the DFS Symbol Description Speed Grade Units 5 4 Min Max Min Max Input Frequency Ranges 2 FCLKIN CLKIN_FREQ_FX Frequency for the CLKIN input...

Page 47: ...The time from deassertion at the DCM s Reset input to the rising transition at its LOCKED output The DFS asserts LOCKED when the CLKFX and CLKFX180 signals are valid If using both the DLL and the DFS...

Page 48: ...for a given CLKIN clock period where T CLKIN clock period in ns If using CLKIN_DIVIDE_BY_2 TRUE double the effective clock period CLKIN 60 MHz INTEGER 10 TCLKIN 3 ns steps CLKIN 60 MHz INTEGER 15 TCLK...

Page 49: ...of CLK 0 5 ns TDNADSU Setup time on DIN before the rising edge of CLK 1 0 ns TDNADH Hold time on DIN after the rising edge of CLK 0 5 ns TDNARSU Setup time on READ before the rising edge of CLK 5 0 10...

Page 50: ...to FPGA input pins and interconnect re enabled 3 7 to 109 s TAWAKE_GWE1 Rising edge of the AWAKE pin until write protect lock released on all writable clocked elements using sw_clk InternalClock and...

Page 51: ...300 ns TICCK 3 The time from the rising edge of the INIT_B pin to the generation of the configuration clock signal at the CCLK output pin All 0 5 4 s Notes 1 The numbers in this table are based on the...

Page 52: ...5 ns TCCLK7 7 Commercial 178 357 ns Industrial 168 ns TCCLK8 8 Commercial 156 313 ns Industrial 147 ns TCCLK10 10 Commercial 123 250 ns Industrial 116 ns TCCLK12 12 Commercial 103 208 ns Industrial 97...

Page 53: ...11 37 MHz FCCLK17 17 Commercial 6 80 13 74 MHz Industrial 14 61 MHz FCCLK22 22 Commercial 8 80 18 44 MHz Industrial 19 61 MHz FCCLK25 25 Commercial 10 00 20 90 MHz Industrial 22 23 MHz FCCLK27 27 Comm...

Page 54: ...h 7 ns Hold Times TCCD The time from the rising transition at the CCLK pin to the point when data is last held at the DIN pin Master 0 0 ns Slave 1 0 ns Clock Timing TCCH High pulse width at the CCLK...

Page 55: ...point when a logic level is last held at the RDWR_B pin 0 ns Clock Timing TCCH The High pulse width at the CCLK input pin 5 ns TCCL The Low pulse width at the CCLK input pin 5 ns FCCPAR Frequency of...

Page 56: ...50 TDCC Setup time on DIN data input before CCLK rising edge See Table 50 TCCD Hold time on DIN data input after CCLK rising edge See Table 50 TDH TDSU Command msb TV TCSS 1 1 1 INIT_B M 2 0 TMINIT T...

Page 57: ...t hold time ns TV SPI serial Flash PROM data clock to output time ns fC or fR Maximum SPI serial Flash PROM clock frequency also depends on specific read command used MHz Notes 1 These requirements ar...

Page 58: ...Address A 25 0 outputs valid after CCLK falling edge See Table 50 TDCC Setup time on D 7 0 data inputs before CCLK rising edge See TSMDCC in Table 51 TCCD Hold time on D 7 0 data inputs after CCLK ris...

Page 59: ...s only BYTE to output valid time 3 ns Notes 1 These requirements are for successful FPGA configuration in BPI mode where the FPGA generates the CCLK signal The post configuration timing can be differe...

Page 60: ...TCK pin to the point when data is last held at the TDI pin All functions except those shown below 0 ns Configuration commands CFG_IN ISC_PROGRAM 3 5 TTCKTMS The time from the rising transition at the...

Page 61: ...r LVCMOS15 18 in Table 11 Added reference to VCCAUX in Simultaneously Switching Output Guidelines Removed DNA_RETENTION limit of 10 years in Table 14 since number of Read cycles is the only unique lim...

Page 62: ...I O pin Most pins can be paired together to form differential I Os IO_ IO_Lxxy_ INPUT Unrestricted general purpose input only pin This pin does not have an output structure differential termination r...

Page 63: ...e application AWAKE is available as a user I O pin SUSPEND AWAKE JTAG Dedicated JTAG pin 4 per device Not available as a user I O pin Every package has four dedicated JTAG pins These pins are powered...

Page 64: ...84 package becomes CSG484 when ordered as the Pb free option The mechanical dimensions of the standard and Pb free packages are similar as shown in the mechanical drawings provided in Table 61 For add...

Page 65: ...d the die junction temperature per watt of power consumption The junction to board JB value similarly reports the difference between the board and junction temperature The junction to ambient JA value...

Page 66: ...I O 0 IO_L10P_0 A14 I O 0 IP_0 A15 INPUT 0 IO_L06P_0 VREF_0 A16 VREF 0 IO_L06N_0 A17 I O 0 IP_0 A18 INPUT 0 IO_L07N_0 A19 I O 0 IO_0 A20 I O 0 IO_L30P_0 B3 I O 0 IO_L28P_0 B4 I O 0 IO_L24P_0 B6 I O 0...

Page 67: ...DUAL 1 IP_L27P_1 J21 INPUT Table 63 Spartan 3A DSP CS484 Pinout Cont d Bank Pin Name CS484 Ball Type 1 IP_L27N_1 J22 INPUT 1 IO_L29P_1 A16 K16 DUAL 1 IP_L23N_1 K17 INPUT 1 IO_L24N_1 K18 I O 1 IO_L24P...

Page 68: ...O 2 IP_2 AB15 INPUT 2 IO_L22N_2 DOUT AB16 DUAL 2 IO_L23P_2 AB17 I O 2 IO_L23N_2 AB18 I O Table 63 Spartan 3A DSP CS484 Pinout Cont d Bank Pin Name CS484 Ball Type 2 IO_L27P_2 AB19 I O 2 IO_L30N_2 AB20...

Page 69: ...3 J6 INPUT 3 IP_L12N_3 VREF_3 J7 VREF 3 IO_L19P_3 LHCLK2 K1 LHCLK Table 63 Spartan 3A DSP CS484 Pinout Cont d Bank Pin Name CS484 Ball Type 3 IO_L17P_3 K2 I O 3 IO_L17N_3 K3 I O 3 IO_L13P_3 K4 I O 3 I...

Page 70: ...GND GND GND H7 GND GND GND H8 GND GND GND H10 GND GND GND H12 GND GND GND H14 GND GND GND H16 GND Table 63 Spartan 3A DSP CS484 Pinout Cont d Bank Pin Name CS484 Ball Type GND GND H19 GND GND GND J9...

Page 71: ...CCAUX VCCAUX VCCAUX T13 VCCAUX VCCAUX VCCAUX V5 VCCAUX VCCAUX VCCAUX V18 VCCAUX Table 63 Spartan 3A DSP CS484 Pinout Cont d Bank Pin Name CS484 Ball Type VCCAUX VCCAUX W11 VCCAUX VCCINT VCCINT G7 VCCI...

Page 72: ...64 User I Os Per Bank for the XC3SD1800A in the CS484 Package Package Edge I O Bank Maximum I Os and Input Only All Possible I O Pins by Type I O INPUT DUAL VREF 1 CLK Top 0 77 49 13 1 6 8 Right 1 78...

Page 73: ...INT I O L23P_0 GND VCCAUX GND H I O L11N_3 I O L14P_3 I O L05P_3 I O L05N_3 I O L10P_3 I O L10N_3 GND GND VCCINT GND VCCINT J I O L14N_3 VREF_3 VCCO_3 INPUT L16P_3 INPUT L16N_3 VCCO_3 INPUT L12P_3 INP...

Page 74: ...ND VCCINT GND VCCINT GND I O L18N_1 RHCLK1 I O L21P_1 IRDY1 RHCLK6 VCCAUX I O L19N_1 TRDY1 RHCLK3 GND I O L17N_1 A9 M VCCINT GND VCCINT GND VCCAUX I O L13P_1 A2 I O L18P_1 RHCLK0 I O L15N_1 A7 I O L15...

Page 75: ...0 K16 I O 0 IP_0 J10 INPUT 0 IO_L43P_0 J11 I O 0 IO_L39P_0 J12 I O 0 IP_0 J13 INPUT 0 IO_L25N_0 GCLK5 J14 GCLK 0 IP_0 J15 INPUT 0 IO_L12P_0 J16 I O 0 IP_0 VREF_0 J17 VREF 0 IO_L47N_0 H9 I O 0 IO_L46N_...

Page 76: ...3P_0 B15 I O 0 IO_L19N_0 B17 I O 0 IO_L18P_0 B18 I O 0 IO_L15P_0 B19 I O 0 IO_L14P_0 VREF_0 B20 VREF Table 66 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Cont d Bank XC3SD1800A Pin Name FG676 Ball...

Page 77: ...e 66 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Cont d Bank XC3SD1800A Pin Name FG676 Ball Type 1 IO_L25N_1 A3 R22 DUAL 1 IP_L28P_1 VREF_1 R23 VREF 1 IP_L28N_1 R24 INPUT 1 IO_L29P_1 A8 R25 DUAL 1...

Page 78: ...UAL 1 IO_L02N_1 LDC0 AD25 DUAL 1 IO_L05P_1 AD26 I O 1 IO_L03P_1 A0 AC23 DUAL Table 66 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Cont d Bank XC3SD1800A Pin Name FG676 Ball Type 1 IO_L03N_1 A1 AC2...

Page 79: ...DUAL 2 IO_L22P_2 D7 AE10 DUAL 2 IO_L24N_2 D4 AE12 DUAL Table 66 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Cont d Bank XC3SD1800A Pin Name FG676 Ball Type 2 IO_L26N_2 GCLK15 AE13 GCLK 2 IO_L28N_...

Page 80: ...Y19 VREF 2 IP_2 W18 INPUT 2 IP_2 AA8 INPUT 2 VCCO_2 W11 VCCO 2 VCCO_2 W16 VCCO Table 66 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Cont d Bank XC3SD1800A Pin Name FG676 Ball Type 2 VCCO_2 AE5 VCC...

Page 81: ...L26P_3 M8 I O 3 IO_L21N_3 M9 I O 3 IO_L21P_3 M10 I O 3 IO_L25N_3 L3 I O 3 IO_L25P_3 L4 I O Table 66 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Cont d Bank XC3SD1800A Pin Name FG676 Ball Type 3 IO...

Page 82: ...W8 GND GND GND W14 GND GND GND W19 GND GND GND W24 GND GND GND V3 GND GND GND U10 GND GND GND U13 GND GND GND U17 GND Table 66 Spartan 3A DSP FG676 Pinout for XC3SD1800A FPGA Cont d Bank XC3SD1800A P...

Page 83: ...XC3SD1800A FPGA Cont d Bank XC3SD1800A Pin Name FG676 Ball Type VCCAUX VCCAUX T22 VCCAUX VCCAUX VCCAUX P17 VCCAUX VCCAUX VCCAUX N10 VCCAUX VCCAUX VCCAUX L5 VCCAUX VCCAUX VCCAUX K13 VCCAUX VCCAUX VCCAU...

Page 84: ...ur I O banks on the FG676 package The AWAKE pin is counted as a dual purpose I O Table 67 User I Os Per Bank for the XC3SD1800A in the FG676 Package Package Edge I O Bank Maximum I Os and Input Only A...

Page 85: ...P_0 INPUT K INPUT L24N_3 I O L23N_3 I O L23P_3 I O L22N_3 I O L22P_3 I O L18P_3 I O L13P_3 I O L05N_3 I O L05P_3 GND I O L43N_0 I O L39N_0 VCCAUX L GND VCCO_3 I O L25N_3 I O L25P_3 VCCAUX GND I O L18N...

Page 86: ...1 I O L35P_1 A10 M VCCINT GND VCCINT I O L39N_1 A15 I O L39P_1 A14 I O L34N_1 RHCLK7 I O L42P_1 A16 I O L37N_1 VCCO_1 INPUT L36N_1 I O L33N_1 RHCLK5 INPUT L32N_1 INPUT L32P_1 N VCCINT VCCINT GND VCCAU...

Page 87: ...LK 0 IP_0 J15 INPUT 0 IO_L12P_0 J16 I O 0 IP_0 VREF_0 J17 VREF 0 IO_L47N_0 H9 I O 0 IO_L46N_0 H10 I O 0 IO_L35N_0 H12 I O 0 IP_0 H13 INPUT 0 IO_L16N_0 H15 I O 0 IO_L08P_0 H17 I O 0 IP_0 H18 INPUT 0 IO...

Page 88: ...0 B23 I O 0 IO_L51P_0 A3 I O 0 IO_L45P_0 A4 I O 0 IO_L38P_0 A8 I O Table 68 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Cont d Bank XC3SD3400A Pin Name FG676 Ball Type 0 IO_L36P_0 A9 I O 0 IO_L33P...

Page 89: ...O 1 IP_L36N_1 N23 INPUT 1 IO_L33N_1 RHCLK5 N24 RHCLK 1 IP_L32N_1 N25 INPUT 1 IP_L32P_1 N26 INPUT Table 68 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Cont d Bank XC3SD3400A Pin Name FG676 Ball Typ...

Page 90: ...02P_2 M2 Y7 DUAL 2 IO_L05N_2 Y9 I O Table 68 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Cont d Bank XC3SD3400A Pin Name FG676 Ball Type 2 IO_L12P_2 Y10 I O 2 IO_L17P_2 RDWR_B Y12 DUAL 2 IO_L25N_2...

Page 91: ...I O 2 IO_L45P_2 AD22 I O 2 IO_L01P_2 M1 AC4 DUAL 2 IO_L08P_2 AC6 I O Table 68 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Cont d Bank XC3SD3400A Pin Name FG676 Ball Type 2 IO_L14P_2 AC8 I O 2 IO_...

Page 92: ...R3 I O Table 68 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Cont d Bank XC3SD3400A Pin Name FG676 Ball Type 3 IO_L37N_3 R4 I O 3 IO_L40P_3 R5 I O 3 IO_L40N_3 R6 I O 3 IO_L45N_3 R7 I O 3 IO_L45P_3...

Page 93: ...EF_3 C1 VREF 3 IO_L02N_3 B1 I O 3 IO_L02P_3 B2 I O 3 IP_L66P_3 AE1 INPUT 3 IP_L66N_3 VREF_3 AE2 VREF Table 68 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Cont d Bank XC3SD3400A Pin Name FG676 Ball...

Page 94: ...D15 GND GND GND D19 GND GND GND C3 GND Table 68 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA Cont d Bank XC3SD3400A Pin Name FG676 Ball Type GND GND C9 GND GND GND C14 GND GND GND C19 GND GND GND C...

Page 95: ...NT VCCINT Y4 VCCINT VCCINT VCCINT Y8 VCCINT VCCINT VCCINT Y11 VCCINT VCCINT VCCINT Y18 VCCINT VCCINT VCCINT Y19 VCCINT VCCINT VCCINT W18 VCCINT Table 68 Spartan 3A DSP FG676 Pinout for XC3SD3400A FPGA...

Page 96: ...four I O banks on the FG676 package The AWAKE pin is counted as a dual purpose I O Table 69 User I Os Per Bank for the XC3SD3400A in the FG676 Package Package Edge I O Bank Maximum I Os and Input Only...

Page 97: ...9P_0 INPUT K INPUT L24N_3 I O L23N_3 I O L23P_3 I O L22N_3 I O L22P_3 I O L18P_3 I O L13P_3 I O L05N_3 I O L05P_3 GND I O L43N_0 I O L39N_0 VCCAUX L GND VCCO_3 I O L25N_3 I O L25P_3 VCCAUX GND I O L18...

Page 98: ...O L35P_1 A10 M VCCINT GND VCCINT I O L39N_1 A15 I O L39P_1 A14 I O L34N_1 RHCLK7 I O L42P_1 A16 I O L37N_1 VCCO_1 INPUT L36N_1 I O L33N_1 RHCLK5 INPUT L32N_1 INPUT L32P_1 N VCCINT VCCINT GND VCCAUX I...

Page 99: ...F10 F18 N C N C IP_0 0 VCCINT VCCINT F18 E6 N C N C IP_0 0 VCCINT VCCINT E6 E9 N C N C IP_0 0 GND GND E9 E20 IP_0 0 IP_0 0 VCCAUX VCCAUX E20 D5 N C N C IP_0 0 VCCINT VCCINT D5 D15 IP_0 0 IP_0 0 GND GN...

Page 100: ...B10 AB17 IP_2 2 IP_2 2 VCCAUX VCCAUX AB17 AB20 IP_2 2 IP_2 2 GND GND AB20 AA8 N C N C IP_2 2 VCCINT VCCINT AA8 AA19 IP_2 2 IP_2 2 GND GND AA19 AC22 N C N C IO_2 2 IO_2 2 AC22 Y3 IP_L54P_3 3 IP_L54P_3...

Page 101: ...69 Corrected VREF pins in XC3S1800A FG676 Table 70 Updated FG676 package footprints for XC3SD1800A FPGA Figure 16 and XC3SD3400A FPGA Figure 17 Minor edits 06 18 07 1 2 Updated for Production release...

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Xilinx DS610, Datasheet

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