Xilinx ChipScope Pro, User Manual

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8 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1: Introduction
Design Flow
The tools design flow ( Figure 1-2 ) merges easily with any standard FPGA design flow that
uses a standard HDL synthesis tool and the ISE implementation tools.
Using ChipScope Pro Cores in the PlanAhead Tool
You can add the ChipScope Pro cores to your design using the PlanAhead tool using one of
two methods:
•
HDL instantiation
•
Netlist insertion
Up to 15 independent ILA, VIO, or ATC2
cores per device Can segment logic and test smaller sections
of a large design for greater accuracy.
Multiple trigger settings
Records duration and number of events
along with matches and ranges for greater
accuracy and flexibility.
Downloadable from the Xilinx Web site
Tools are easily accessible from the
ChipScope Suite
[See Reference 18, p. 225] .
Table 1-2: ChipScope Pro Logic Debug Features and Benefits (Cont’d)
Feature Benefit
X-Ref Target - Figure 1-2
Figure 1-2: ChipScope Pro Tools Design Flow
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