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ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1:
Introduction
You can modify many options in the ILA, VIO, and ATC2 cores without resynthesizing.
However, after changing selectable parameters (such as width of the data port or the depth
of the sample buffer), the design must be resynthesized with new cores.
shows
which design changes require resynthesizing.
System Requirements
Operating System Requirements
The ChipScope Pro operating system requirements are described in the
ISE Design Suite
Installation and Licensing Guide
.
Software Tools Requirements
The Xilinx CORE Generator, ChipScope Pro Core Inserter, IBERT Core Generator, and
CSE/Tcl tools require that ISE implementation tools be installed on your system. (Tcl
stands for Tool Command Language and a Tcl shell is a shell program that is used to run
Tcl scripts.) CSE/Tcl requires the Tcl shell (called
xtclsh)
that is included in the
ChipScope Pro and ISE tool installations.
Note:
The version (including update revision) of the ChipScope Pro tools must match the version
(including update revision) of the ISE tools that is used to implement the design that contains the
ChipScope Pro cores.
Table 1-12:
Design Parameter Changes Requiring Resynthesis
Design Parameter Change
Resynthesis Required
Change trigger pattern
No
Running and stopping the trigger
No
Enabling the external triggers
No
Changing the trigger signal source
No
( 1)
Changing the data signal source
No
( 1)
Changing the ILA clock signal
Yes
Changing the sample buffer depth
Yes
Notes:
1. The ability to change existing trigger and/or data signal sources is supported by the ISE FPGA Editor
tool, regardless of how the ChipScope cores were added to the design.
