ALINX Xilinx Core Board AC6150 User Manual
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the core board. Users can connect the pin headers on the core board and
connect the download and core JTAG ports with DuPont cable. To achieve core
board program download and debug of the FPGA chip without the carrier board.
The following Figure 3-2-3 shows the JTAG interface on the core board:
Figure 2-3: JTAG Interface on the core board
Part 3: DDR3 DRAM
Figure 3-1 detailed part of the DDR3 schematic (For details, please refer to
the schematic provided by us.)
Figure 3-1: DDR3 schematic
