Xerox WorkCentre 385, Service Manual

Page: 154 / 184

WorkCentre 385
Circuit Description
12/98
7 - 20
DA[12:0]
/
ExtMA[27:24]
ExtMBST
ExtMAS[1:0]
ExtMRnW 128~133
135~141
128~131
138
139~140
141
I/O DA[12:0] acts as an output for the 13-bit DRAM address bus. In
external master mode, it acts as an input, in which
ExtMA[27:24] corresponds to the higher 4-bits out of 28-bit
external master address bus ExtMA[27:0]; ExtMBST is burst
mode selection signal;ExtMRnW is R/W control signal; and
ExtMAS[1:0] is memory access size control signal which is
used to inform KS32C6100’s memory controller that the exter-
nal master will access memory in byte (00), halfword (10). Note
the state (11) for ExtMAS[1:0] is not used.
nRAS[5:0] 122~127 O Not row address strobes for Dram banks. The KS32C6100
supports up to six DRAM banks. One nRAS output is provided
for each bank.
nCAS[3:0] 116~118
121
O Not column address strobes for DRAM. The four nCAS outputs
indicate the byte selections whenever a DRAM bank is
accessed.
nDOE 115 O Not output enable for DRAM. Whenever a DRAM access
occurs, the nOE output controls the output enable port of the
specific DRAM.
nDWE 114 O Not write enable for DRAM. Whenever a DRAM access occurs,
the nWE output controls the write enable port of the specific
DRAM.
nSRD[1:0] 144, 146 O Not special I/O read strobe with address latch.
nSWR[1:0] 145, 147 O Not special I/O write strobe with address latch.
ExtMREQ 23 I External master request. The ExtMREQ input signal indicates
that the external master requests to hold KS32C6100 system
bus.
ExtMACK 24 O Acknowledge for external master holding request. This output
signal indicates that the external master holding request has
been accepted.
ExtMnDL 25 I/O External master data latch signal.
Table 2: KS32C6100 Signal Descriptions
Signal PIN No. Type Description
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