Xerox Alto I User Manual Download

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Summary of Contents for Alto I

Page 1: ...iginal description of the Alto Alto A Personal Computer System It includes a complete description of the Alto I and Alto II hardware and of the standard microcode I 24 II 3 Xerox Corporation 1978 1979...

Page 2: ...Ethernet 7 1 Programming Characteristics 7 2 Ethernet Hardware 7 3 Ethernet Microcode 8 0 Control RAM ROM and S Registers 8 1 RAM Related Tasks 8 2 Processor Bus and ALU Interface 8 3 Microinstruction...

Page 3: ...nstruction set for which emulation microcode is supplied in the microinstruction ROM is described in section 3 0 64K 16 bit words of 850ns error corrected semiconductor memory expandable to 256K 1K mi...

Page 4: ...enby The members of EOD SPG who worked on the project are Doug Stewart Ron Cude Ron Freeman Jim Leung Tom Logan Bob Nishimura Abbey Silverstone Nathan Tobol and Ed Wakida This hardware manual has had...

Page 5: ...IR The registers are connected to the memory and to an ALU with a 16 bit parallel bus For historical reasons the sand M registers are viewed as part of the microinstruction RAM and are described in s...

Page 6: ...r I 5 RSEL 4 Constant 3 ROM BS 4 256 x 16 Processor Bus IR ALU Bus MAR Memory Address Bus II 16 Decode Control Figure 1 Processor DataPaths Monitor Transceiver I Drive I I I I I Display Ethernet Contr...

Page 7: ...ntrols the sN74181 ALU This device can do a total of 48 arithmetic and logical operations most of which are relatively useless The 4 bit field is mapped by a PROM into the 16 most useful functions ALU...

Page 8: ...ied by each field except BLOCK are interpreted identically by all tasks but the interpretation of the second eight depends on the active task The task independent functions are given below the task sp...

Page 9: ...Main memory references are handled differently on Alto I and Alto II It is however possible to write most microcode so that it will operate correctly on both machines BASICS Memory is addressed by a...

Page 10: ...e reference is a fetch of the word addressed by MAR During cycle 6 if BS 5 MD the odd word of the doubleword addressed by MAR is delivered If MD is referenced during cycle 6 it also must have been ref...

Page 11: ...er MD Alto II MAR ANY REQUIRED OPTIONAL MD whatever immediately by another Alto II MAR ANY REQUIRED REQUIRED MD whatever SUSPEND MAR At Y Alto II MAR ANY REQUIRED USPEND SUSPEND whereever MD whereever...

Page 12: ...o signal that a memory reference should go to the alternate bank the microinstruction which loads MAR must also contain F2 6 MD The microassembler will generate this conbination of functions for a cla...

Page 13: ...K or the RAM to 3K see section 8 BRANCHING The microprocessor offers a limited branching capability which although somewhat cumbersome has proven adequate for chores undertaken by Alto microcode The b...

Page 14: ...R A MPCRAM S 4 E 4 N K 16x12 T 2 10 I Address Modification Logic CRAM Address I _J I MPX I It Address Address Control Control Next Microinstruction RAM ROM Address Bus 1Kx32 1Kx32 or or 3Kx32 2Kx32 D...

Page 15: ...rrently running task to remove its wakeup signal This function is not accomplished by the Alto microprocessor but rather by the individual device interfaces Task switches must occur only at times when...

Page 16: ...ions are available for transferring contents of accumulators to and from memory registers and for performing arithmetic and logical operations among accumulators The notation AC n is often used to ref...

Page 17: ...AFunc 0 NEG AFunc 1 MOV AFunc 2 INC AFunc 3 ADC AFunc 4 SUB AFunc 5 ADD AFunc 6 AND AFunc 7 AugmentedFunc 8 12 113 DISP x 0 Page 0 addressing X 1 PC relative addressing X 2 Base register AC2 X 3 Base...

Page 18: ...specifies one of the four accumulators DestA C afor ACO DestAC 1 for Ac1 etc The MFunc field specifies one of two operations Mnemonic MFunc Action LDA STA 1 2 This operation loads an accumulator from...

Page 19: ...he complement of c The function generator is controlled by the AFUnc field various values will be described below It takes two 16 bit numbers and a carry input and generates a 16 bit Result and a carr...

Page 20: ...To From Memory D tAC es Accumulators Carry SrcAC DestAC Carry Generator 1 16 16 Function Generator 1 16 Shifter 1 16 Skip Sensor 1 16 Governed by NL Y I Figure 4 ee Instruction Execution...

Page 21: ...enerator otherwise supply the specified value MOVE The function generator passes Ac srcAc and the carry bit unaffected INCREMENT The Result produced is AC SrcAC 1 the carry is complemented if Ac srcAc...

Page 22: ...77B is the largest positive number and 100000B the largest negative The code generated by Bcpl looks like LDA 0 4 2 LDA 1 5 2 ADCL 1 0 SZC JMP falsePart JMP truePart Pick up a Pick up b Subtract and c...

Page 23: ...he Alto s standard instruction set by implementing additional functions in software which is dispatched to via TRAPVEC or in microcode which is dispatched to via a RAM trap An appendix tabulates the s...

Page 24: ...ord mask table be set up starting at MASKTAB 460B in page l rv MAsKTAB n 21 n 1 1 ns 15 The format of an Alto font designed for use with CONVERT is given below names of font files in this format conve...

Page 25: ...d ACI DBA AND 17B Ac2 unchanged Ac3 the width of the character in bits If the character requires an extension CONVERT returns does not skip Ac3 contains the pseudo character code for the extension and...

Page 26: ...hese instructions are potentially time consuming and keep their state in the AC S they are interruptable If an interrupt occurs the PC is decremented by one and the AC S contain the intermediate state...

Page 27: ...of the line the interrupt latency can be as much as 1 bit time without errors JMPRAM 610l0B Jump to RAM see section 8 S for details RDRAM Switches the emulator task micro PC to another microinstructi...

Page 28: ...This instruction writes the same memory location with two different values in quick succession rv AC3 ACO rv AC3 ACO xor Acl ACO ACO xor ACI 61024B Bit boundary block transfer An instruction for movi...

Page 29: ...rupt BITBLT will finish its job This isthe reason w4y Aclmustbe zero when starting the instruction DEFINITIONS A bit map is a region of memory defined by BCA and BMR where BCA is the base core address...

Page 30: ...ts is repeated The pattern is specified by four words GrayO through Gray3 These give the patterns to write into the destination block where called for one gray word per scan line The words will align...

Page 31: ...40 cycles Total for a typical character 8 wide by 14 high approximately 1500 cycles These timings all in units of Alto microinstruction cycles and do include all memory wait time and do not include an...

Page 32: ...etween instructions or during long instructions in which case the instruction s intennediate state is saved in the accumulators and PC is backed up so that the interrupted instruction is re executed w...

Page 33: ...nested interrupts from higher priority channels where the priority is determined by software This is accomplished by turning off all lower priority channels and re enabling interrupts which were disab...

Page 34: ...el s ACTIVE bit is 0 when viewed from non interrupt level u1 en u1 e channel is not in use The code below searches ACTIVE for the highest priority free channel It is careful not to assign the parity i...

Page 35: ...ze the cost in additional microinstructions in the emulator main loop of the most common case where the interrupt system is enabled and no interrupts are pending When a bit appears in hTWW while the i...

Page 36: ...s bus bits 0 5 6 and 7 into NEXT 6 9 which does a first level instruction dispatch The high order bits of IR cannot be read directly but the displacement field of IR 8 low order bits may be read with...

Page 37: ...ts the SKIP flip flop if appropriate see section 3 1 The emulator microcode increments PC by 1 at the beginning of the next emulated instruction if SKIP is set using BUS SKIP ALUF 13B IR clears SKIP N...

Page 38: ...ock wait 16 HTAB bits before displaying information from memory Bits 8 15 NWRDS Each scan line in this block is defined by NWRDS 16 bit words NWRDS must be even In order to skip space on the screen wi...

Page 39: ...the buffer empty and clears the DWT block flip flop at the beginning of horizontal retrace for every scan line 4 3 Display Controller Microcode The display controller microcode is divided into three t...

Page 40: ...a DCB The cursor may be removed from view in a number of ways The most efficient in terms of processing time is to set the x coordinate to 1 The cursor hardware consists of a 16 bit shift register whi...

Page 41: ...Register f 1 word Buffer Video f Display Digital Shift Register Mixer Bit Clock Sync Sync _ Generator Buffer Control Figure 5 Display Control Pointer to next DeB I 1 I J Resol BkGnd Horizontal Tab Wor...

Page 42: ...boards earlier Alto lIs have ADL keyboards which are somewhat larger and have columns of function keys on the left and right sides MICROS TCHKEYBOARD Bit KBDAD 177034B KBDAD 1 177035B KBDAD 2 177036B...

Page 43: ...ILIN are depressed keys correspond to O s in memory UfILIN 8 UfILIN 9 UfILIN 10 UfILIN ll UfILIN 12 5 4 External Device Interface Key 0 left most Key 1 Key 2 Key 3 Key 4 right most Two memory location...

Page 44: ...ion if present and moves the carriage to the left margin UTILOUT 2 Ribbon bit When this bit is 1 the ribbon is up in printing position when 0 it is down UTlLOUT 3 Daisy strobe bit Toggling this bit ca...

Page 45: ...nverted Location UTILIN 177030B UfILIN I ONLINE UTILIN 2 NOPAP UfILIN 3 READY Location UTlLOUT 177016B UfILOUT O RFFED UfILOUT 1 CLEAR UTlLOUT 2 RLTER UfILOUT 3 PICLK UTlLOUT 4 PRINT UfILOUT 5 SPP UTl...

Page 46: ...ficient to determine precisely where the parity error occurred The intent of the collection is to save values of the R registers most likely to be used as a source of memory addresses Alto II Address...

Page 47: ...f the memory configuration switch This switch is located on the front of Alto 1 s and at the top of the backplane of the Alto II The current setting of the switch is reported in bit 6 of UTILIN locati...

Page 48: ...K chips Le an Alto with extended memory this means BANK MAR O Subgroup chip positions 7 6 5 4 3 2 1 o 81 90 71 80 61 70 51 60 41 50 31 40 21 30 11 20 Nearest the edge connector The location of the bit...

Page 49: ...thm above at 0 The syndromeMapping maps a 6 bit number range 0 to 63 into the number of the bad bit 0 to 38 or 1 if the syndrome is incorrect 0 1 2 3 4 5 6 7 0 38 37 36 1 35 1 18 1 syndrome values 0 t...

Page 50: ...ler records three independent data blocks in each sector The first is two words long and is intended to include the address of the sector This block is called the Header block The second block is eigh...

Page 51: ...rst word is a pointer to the next disk command block in this chain A 0 means that this is the last disk command block in the chain When the command is complete the disk controller stores its status in...

Page 52: ...nate immediately after the correct cylinder position is reached before any data is transferred xOR ed with A 14 to yield hardware disk number SIGNIFICANCE Current sector number One can tell whether st...

Page 53: ...ask Error Interrupt bit mask Reserved Disk address Disk Command Block KCB Header Action I Seek Seek Fail 521 522 523 524 Label Data Action Action I 0 Read 1 Check 2or3 Write Not Data Rdy Late Idle Poi...

Page 54: ...BLK DeB pointer is set to 0 and KBLK 2 current disk address is set to 1 The effect of this is to cause the disk controller to abandon the current disk command chain and to forget where the disk arm is...

Page 55: ...task specific Fl S four of which activate bus destination registers and the remaining three of which provide useful pulses and fourth by two task specific BS S The following tables describe the effect...

Page 56: ...record number where MAP O 0 MAP l 2 MAP 2 3 MAP 3 1 NEXT NEXT OR if current command wants data transfer then 1 else 0 NEXT NEXT OR if disk not ready to accept command then 1 else 0 NEXT NEXT OR if fa...

Page 57: ...is used to connect all types of Ethernet interfaces to the Ether so the transceiver design is not specific to the Alto and will not be described here The following sections describe the programming c...

Page 58: ...the left byte and the status of the interface in the right byte The possible values of the microcode status byte EPLoc 0 7 and their meanings are EPLoc 0 7 0 EPLOc 0 7 1 EPLOc 0 7 2 Input done If the...

Page 59: ...C The microcode never modifies the buffer count or pointer locations To keep the receiver listening as much of the time as possible if EICLoe is non zero when an output command is issued the microcode...

Page 60: ...egister fills up again before the word has been transferred from the write register to the FIFO data has been lost and the nput gata late flip flop is set Ethernet transmitters accumulate a 16 bit grc...

Page 61: ...buffer overrun 3 Load overflow 4 Zero length buffer 5 Reset by software I 6 Impossible microcode condition 7 377b Reserved Alto Processor Bus 1 Interface Buffer 16 16 words 16 II Output Shifter Write...

Page 62: ...hardware says that the packet has ended or the buffer overflows in either case the input operation terminates and posts An output command SIO with AcO 14 1S 1 causes the microcode to compute a random...

Page 63: ...FCT EBFCT ECBFCT EISFCT Fl 15B F2 10B F2 llB F2 12B F2 13B F2 14B F2 15B F2 16B Countdown Wakeup function Sets a flip flop in the interface that will cause a wakeup to the Ether task on the next tick...

Page 64: ...erencing MD in the same microinstruction during the third or fourth cycle of a memory reference On Alto II the hardware automatically stops the clock for one cycle when necessary however due to a desi...

Page 65: ...esponse to certain values of the FI and BS fields of the microinstruction Not all tasks are likely to be interested in these functions Moreover not all tasks will have the appropriate values of the F1...

Page 66: ...control RAM word The ALU output during the microinstruction following the WRTRAM will be written into the low order half This protocol mates well with doubleword main memory reads 8 3 Microinstructio...

Page 67: ...uting in RaMO RAMO RAMO ROMO In the 2K ROM configuration which includes 1K of RAM If currently and NEXT lJ 0 then else executing in go to NEXT in go to NEXT in RaMO RAMO ROMI RaMI RaMO RAMO RAMO RaMO...

Page 68: ...e control RAM and theri transferring control to that microcode RDRAM 61011B Read from Control RAM Reads the control RAM or ROM halfword addressed by ACI into ACO The microcode is T ACl RDRAM L ALLONES...

Page 69: ...ding of both Rand S registers are controlled by the BS field of the microinstruction Nevertheless there are considerable differences To begin with the M and S registers are active only when a RAM rela...

Page 70: ...RAM What happens is that the last instruction suspends the system clock for one microinstruction and some Alto I memories cannot keep the memory data good for two microinstruction times so a parity e...

Page 71: ...ge this compatibility the file AltoConstsx MU will be maintained the x corresponding to the latest AltoCodex containing definitions and constants for both Alto I and Alto II These can be logically inc...

Page 72: ...the emulator S main loop in the ROM Otherwise control is passed to location PC AND 777B in RAM or ROMI The bank dispatched to is determined by the SWMODE rules described in section 8 4 Warning Some o...

Page 73: ...efore if these memories contain appropriate contents it is not really necessary to go through the full disk or Ethernet bootstrap load sequence since the major purpose of those sequences is to initial...

Page 74: ...mple such a piece of code is required in order to set the reset mode register By convention we reserve a utility area of RAMO for this purpose The normal procedure is to save the contents of this area...

Page 75: ...and the controller has only 16 bits of buffering It has been determined empirically that task latency greater than 20 microinstruction times causes Diablo Model 44 disks to encounter data late errors...

Page 76: ...8 7 CONSTANT 4 BUS 5 ALUCY 6 MD 7 CONSTANT 4 16 7 10 BUS T 11 BUS T l 12 BUS T l 13 BUS SKIP RAM o CPU KSEC KWD EfHER Related 14 BUS T 15 BUS AND NOT T 16 UNDEFINED 17 UNDEFINED 3 SLOCATION 4 SLOCATI...

Page 77: ...ddress Std Microcode Disk status at start of current sector Std Microcode Disk address of latest disk command Std Microcode Sector interrupt bit mask Std Microcode Interval timer time Std Microcode Tr...

Page 78: ...ame Section Emulator 3 KSEC 6 ETHER 7 MRT DWT 4 CURT 4 DHT 4 DVT 4 PART 5 5 KWD 6 APPENDIX D STANDARD TASKS Description Lowest priority Wakeup always true unused unused unused Disk sector task unused...

Page 79: ...AM trap 72400 72777 555 RAM trap 73000 73377 556 RAM trap 73400 73777 557 RAM trap 74000 74377 560 RAM trap 74400 74777 561 RAM trap 75000 75377 562 RAM trap 75400 75777 563 RAM trap 76000 76377 564 R...

Page 80: ...engineering number 0 microcode version 1 doesn t work reliably if some ram related task is running e g the Trident disk returns engineering number 2 microcode version O doesn t work reliably if some...

Page 81: ...face Jto DLS input Alto DLS output 177701 177720 177737 177764 177773 EIALOC EIA interface output bit EIA interface input bit 177776 177776 177777 TV Camera Interface Redactron tape drive Digital Anal...

Page 82: ...to II without additional hardware Contact SPG to get a cable PIN 216540 Tape Controller A two card processor bus interface to MDS and Kennedy tape drives It will handle 1600 bpi phase encoded tapes on...

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