Page 1: ...XIDlS SIGMA 9 COMPUTER Xerox Data Systems Reference Manual ...
Page 2: ...ive 67 CVA 29 Convert by Addition 72 PACK 76 Pack Decimal Digits 83 CVS 28 Convert by Subtraction 73 PLM OA Pull Multiple 97 CW 31 Compare Word 67 PLW 08 Pull Word 96 DA 79 Decimal Add 81 POLP 4F Poll Processor 120 POLR 4F Poll and Reset Processor 120 DC 7D Decimal Compare 82 PSM OB Push Multiple 96 DD 7A Decimal Divide 82 DH 56 Divide Halfword 63 PSW 09 Push Word 95 DL 7E Decimal Load 80 RD 6C Re...
Page 3: ...ice 6 50 XDS SIGMA 9 COMPUTER REFERENCE MANUAL FIRST EDITION 90 17 33A October 1970 Xerox Data Systems 701 South Aviation Boulevard EI Segundo California 90245 1970 Xerox Data Systems Inc Printed in U S A ...
Page 4: ...BLICATIONS Title XDS Sigma Glossary of Computer Terminology XDS Symbol Meta Symbol Reference Manual Sigma 5 7 Computers XDS Macro Symbol Reference Manual Sigma 5 7 Computers Publ ication No 90 09 57 90 0952 90 15 78 ...
Page 5: ...UCTION REPERTOIRE 44 Load Store Instructions ___________ Analyze Interpret Instructions _________ Fixed Point Arithmetic Instructions ______ Comparison Instructions ___________ Logical Instructions _____________ Shift Instructions _____________ Floating Point Shift ___________ Zoned Decimal Numbers _________ Decimal Accumulator___________ Decimal Instruction Format_________ Illegal Digit and Sign ...
Page 6: ...UPT 130 ADDRESS STOP 130 D SYSTEM RELIABILITY AND MAINTAINABILITY 166 SELECT ADDRESS 131 DISPLAY switch 131 System Maintainabi Iity Features 166 INSTR ADDR 131 CPU Features 167 DISPLAY Indicator 132 Main Memory Features 169 DISPLAY FORMAT 132 FORMAT SEL 132 Multiplexor Input Output Processor MIOP Features 169 DATA 132 STORE 132 High Speed RAD I O Processor HSRIOP Features 170 COMPUTE 132 Maintenan...
Page 7: ...ating Point Number Representation 74 4 Summary of SIGMA 9 Trap Locations 34 12 Condition Code Settings for Floating Point 5 TCe Setting for Instruction Exception Instructions 76 Trap XI 4D 41 13 Status Response for I O Instructions 115 6 Registers Changed at Time of a Trap Due to 14 Program Status Doubleword PSD an Operand Access 42 Indi cation 129 7 Status Word 0 52 C l Basic Instruction Timing J...
Page 8: ...i labi lity have been significantly improved over previous SIGMA computers A partitioning feature for example permits faulty units or an entire subsystem consisting of a CPU memory un it lOP and attached peripherals to be isolated from the sys tem for diagnosis and repair whi Ie the primary system continues operation This manual describes the general characteristics and features system organ izati...
Page 9: ...ude Diagnostic programs with capabilities for sys tem verification and testing to determine the faulty unit unit functional testing to deter mine the specific function of a unit that is faulty and fault location diagnosing to analyze what physical component is malfunctioning Extensive error logging When a fault is de tected system status and fault information are available for program retrieval an...
Page 10: ...ic display has standard char acter generator vector generator and c lose ups as well as iight pen and alphanumeric function keyboard Card equipment Reading speeds up to 1500 cards per minute punching speeds up to 300 cards per minute intermixed binary and EBCDIC card codes Line printers Fully buffered with speeds up to 1 500 lines per minute 132 print positions with 64 characters Keyboard printers...
Page 11: ...n extra instruction execution 4 Input Output Capabi lities fime Sharing Features INPUTjOUTPUT CAPABILITIES Multiplexing Input Output Processor MIOP Once initialized I o processors operate independently of the CPU leaving it free to provide faster response to system needs The MIOP requires minimal interaction with the CPU by using channel command doublewords which per mit both command chaining and ...
Page 12: ...e of the disarm disable fea ture makes programmed dynamic reassignment of priorities quick and easy even while a real time process is in progress In establ ishing a con figuration for the system each group of up to 16 interrupt levels can have its prior ity assigned in different ways to meet the specific needs of a problem the way interrupt levels are programmed is not affected by the priority ass...
Page 13: ...SIGMA 9 Computer System vi ...
Page 14: ...tions Input Output Because of its wide range of capacities and speeds the SIGMA 9 I O system simultaneouslysatisfiesthe needs of many different application areas economically both in terms of equipment and programming 6 Multiusage Multiprocessing Features Instruction Set The large SIGMA 9 instruction set provides the computational and data handling capabilities required for widely differing applic...
Page 15: ...or systems This function provides three basic features 1 Control of the External Direct Input Output bus External DIO used for controlling system 2 maintenance and special purpose units such as AID converters Central control of system partitioning 3 Interprocessor interrupt connection a lowing one processor to directly signal another pro cessor that an action is to be taken SHAREDINPUT OUPUT Provi...
Page 16: ... MEMORY CONTROL STORAGE The CPU has three high speed integrated circuit memories for storage of a memory map memory access protection codes associated with the memory map and memory write protection codes This storage can be changed when the computer is in the master or master protected mode Memory Map Two terms are essenti al to a proper under standing of the memory mapping concept virtual addres...
Page 17: ...r blocks 2 clocks r I J Power fail safe t 4 byte interface j option Floating point arithmetic I O bus 1 1 Multi 1 device 1 1 controller Io __ __ J j _ __ __1 __ 11 0 devicel I O device 1 I 1 1 I 1 I a I 15 I 1 _____ External interface 8 interrupt levels I O bus __1__ __ __ Single Single I device 1 device j I I O devi ce I I I O devi ce 1 L _____ I ____ __i__ I Removable disk unit I I I I 2 spi ndI...
Page 18: ... Registers oIndirect Address Flag o III IIII I Operation Code Field 1 7 DIIJ General Register Designator 8 11 OJ Index Register Designator 12 14 Reference Address Field I1111111111111111111 15 31 Memory I 31 digit Decimal Accumu lator I O Processors I I I I Read Write Direct I 1 Interrupts I I Priority Interrupt System I Write Direct I PROGRAM STATUS DOUBLEWORD OJ Condition Code o 3 ill Floating p...
Page 19: ...s protection codes apply to the slave mode program if mapping is in effect and all privileged operations are prohibited Privileged opera tions are those relating to input output and to changes in the basic control state of the computer All privileged operations are performed in the master or master protected mode by a group of privileged instructions Any attempt by a program to execute a privilege...
Page 20: ... 8 11 Description This bit position indicates whether indirect ad dressing is to be performed Indirect addressing one level only is performed if this bit position contains a 1 and is not performed if this bit posi tion contains a O Operation Code This 7 bit field contains the code that des ignates the operation to be performed See the inside front and back covers as well as Append ix B for complet...
Page 21: ...in the unit that is all ports in a given memory unit provide access to both banks within that unit MEMORY BANK A memory bank is the basic functionally independent ele ment of the memory system It consists of magnetic storage elements drive and sense electronics control timing and data registers A bank consists of 16 384 memory locations Each location stores a 32 bit information word instruction or...
Page 22: ...thin 14 Main Memory all memory units The size of real memory ranges from a minimum of 128K words to 512K words The 512K maximum size limitation is physical i e based on maximum cable length considerations rather than logical Real memory addressing space is over 4 million 222 words HOMESPACE In a SIGMA 9 multiprocessing system all processors address memory in the same manner However since the CPUs ...
Page 23: ...ny instruction except a trap or interrupt instruction that has bit position 10 equal to O See 20 Bit Reference Address below For real and virtual addressing the reference address is the address contai ned wi thi n bits 15 31 of the instruction itself For real extended ad dressing the reference address is comprised of bits 16 31 of the instruction concatenated with bits 42 47 of the pro gram status...
Page 24: ...ce if required 16 Main Memory B CONTROL FLOW yes Figure 4 Addressing Logic DATA FLOW Reference Address Instruction Word Address Write locks lst 128K words only Actual Address r Memory Address Register Main Memory ...
Page 25: ... takes place All actual addresses are 21 22 23 or 24 bits as required to address a doubleword word halfword or byte Effective Address The effective address is defined as the final virtual address computed for an instruction output from the address generator in Figure 4 The effective address is usually used as the virtual address of an opercmd location or result destination However some instruction...
Page 26: ...re is also invoked 7 Virtual addressing may be used in all modes and is specified when PSD 9 is a 1 REAL EXTENDED ADDRESSING Real extended addressing is similar to real addressing in that there is a direct relationship between the effective virtual address of each instruction and the actual address Real extended addressing faci Iitates operating wi th mem ories larger than 128K words It permits th...
Page 27: ...y reference memory fully without the use of the extended address field in the PSD The only exception is the 22 bit word address used for indirect addressing Branching and Branch Addresses The Extension Address field of the program status doubleword PSD bits 42 47 may be loaded at the time a new PSD is loaded by an XPSD or LPSD instruction This field is modified automatically by branch instructions...
Page 28: ...tion that is if it is a byte operation the dis placement is Iined up so that its low order bit is al igned with the least significant bit of the 34 bit instruction reg ister The displacement is shifted one bit to the left of this positi on for a halfword operation two bits to the left for a word operation and three bits to the left for a double word operation An addition process then takes place t...
Page 29: ...ield in the instruction stored in memory The instruction is brought into the instruc tion register and if the value of the reference address field is greater than 15 it is converted from a 19 bit reference address to a 24 bit actual address by the memory map The 17 low order bits of the main memory location pointed to by the actual address labeled reference address 2 then replaces reference addres...
Page 30: ...of three types differentiated by bit 0 and bit 15 of the direct address If bit 0 is a 0 bits 10 to 31 are used as the 22 bit direct address If bit 0 is a 1 and bit 15 is a 0 then bits 16 31 are concatenated with 6 leading zeros to form a 22 bit 22 Mai n Memory direct address When bit 0 is a 1 and bit 15 is a 1 bits 16 31 are concatenated with the contents of the Extension Register to form a 22 bit...
Page 31: ...ndirect addressing replaces reference address with direct address Halfword operation indexing alignment Effective virtual address The 8 high order bits of the effective address are replaced with 13 bit page address N from memory map Final memory address which is the actual address of halfword location containing the effective halfword r 24 bit actual address III III r Figure 7 Generation of Actual...
Page 32: ... if bit 0 0 Address used if bit 0 1 and bit 15 0 Address used if bit 0 1 and bit 15 1 Displacement aligned for halfword indexing Final effective address If bit 15 1 If bit 15 0 e e e e e e r r r r r r r r r r r r r r 00 10 11112 13 14 1516 17 18 19120 2122 23 24 25 26 27128 29 30 31 Figure 8 Generation of Effective Virtual Address Real Extended Addressing 24 Main Memory ...
Page 33: ...ode When the memory map is in effect all memory references used by the program including instruction addresses whether direct indirect or indexed are referred to as vir tual addresses Virtual addresses in the range 0 through 15 are not used to address main memory instead the 4 low order bits of the virtual address comprise a general register address However if an instruction produces a virtual ad ...
Page 34: ...in the master protected or slave mode and is usi ng the memory map the access protection codes are examined at the time the virtual address is converted into an actual address Then the locks and keys are 26 Main Memory examined to determine whether the program master master protected or slave mode is allowed to alter the contents of the main memory location corresponding to the final actual addres...
Page 35: ...ature that faci Iitates the generation of ASCII character codes When this bit is a 1 ASCII codes are generate d When this bit is a 0 EBCDIC codes are generated Desig nation IA ES ED WK CI II EI MA EA TSF RP Function Instruction address This 17 bit field contains the virtual address of the next instruction to be executed Extension selector In real extended type of addressing this bit indicates whet...
Page 36: ...terrupt permits the testing of special systems programs before the special systems equipment is actually attached to the computer and also permits an interrupt servicing routine to defer a portion of the processing associated with an interrupt level by processing the urgent portion of an interrupt servicing routine triggering a lower priority level for a routine that handles the less urgent part t...
Page 37: ...al interrupts Figure 9 illustrates this with a configuration that a user might establ ish where after the override group the counter group of internal interrupts is given the second highest priority followed by the first group of external interrupts then the input output group of internal interrupts and finally all succeeding groups of external interrupts INTERNAL INTERRUPTS Internal interrupts in...
Page 38: ...UPT button on the processor control panel The control panel interrupt level can thus be triggered by the computer operator allowing him to initiate a specific routine The interrupts in the input output group can be inhibited or permitted by means of bit position 38 II of the program status doubleword If II is a 0 the interrupts in the I o 30 Interrupt System group are allowed to interrupt the prog...
Page 39: ...cation the effective address is generated subject to the current active addressing mode real real extended or virtual If for XPSD bit 10 and bit 0 are equal to a bits 12 31 of the instruction uncondi tionally specify a direct address within the first 1 million 220 words of real memory Since the index field is used for addressing indexing is not possible If bit 10 is equal to a and indirect address...
Page 40: ...hus the instruction can be interrupted between the completion of one iteration oper and execution cycle and the point in time during the next iteration when a memory location or register is modified If an interrupt occurs during this time the current iteration is aborted and the instruction address portion of the program status doubleword remains pointing to the interrupted instruc tion After the ...
Page 41: ...the privileged instructions XPSD or LPSD 3 The floating point significance check trap is masked by a combination of the floating significance FS floating zero FZ and floating normal ize FN TIode control bits see IIFloating Point Arithmetic FaultTrapll FS FZ and FN can be set or cI eared by the execution of any of the following instructions LOAD CONDITIONS AND FLOATING CON TROL LCF LOAD CONDITIONS ...
Page 42: ...ed point AM For all instructions except None arithmetic overflow DW and DH trap occurs after completion of in struction For DW and DH instruction is aborted with memory registers CC1 CC3 and CC4 unchanged 68 44 Floating point At detection arithmetic fault l Charactersiti c None The floating point None overflow instruction is aborted without changing any 2 Divide by zero None registers The conditio...
Page 43: ... abort the instruction being executed at the time that the nonallowed operation is detected and to immediately execute the XPSD instruction in Homespace trap location X 40 A nonallowed operation trap cannot be masked NONEXISTENT INSTRUCTION Any instruction that is not standard on SIGMA 9 is defined as nonexistent This inC udes immediate operand instructions that are indi rectly addressed l in bit ...
Page 44: ...on codes OC and OD and their indirectly addressed forms 8C and 8D are both nonexistent and priv ileged If anyone of these operation codes is used while the CPU is in the slave mode both CCl and CC3 are set 36 Trap System to lis after the current PSD is modified and if bit position 9 of XPSD containsa 1 the program counter is incremented by 10 All other nonexistent operation codes are treated as no...
Page 45: ...r than 215_1 the instruction is aborted with memory and registers unchanged If TS bit 32 of the stack pointer doubleword is set to 0 the CPU traps to Homespace location X 42 If TS is set to 1 the trap is inhibited and the CPU processes the next instruction If execution of the instruction would cause the words W field to become less than 0 or greater than 215 1 the instruction is aborted with memor...
Page 46: ...he value loaded from memory FLOATING POINT ARITHMETIC FAULT TRAP Floating point fault detection is performed after the opera tion called for by the instruction code is performed but before any results are loaded into the general registers Thus the floating point operation that causes an arithmeti c fault is not carried to completion in that the original con tents of the general registers are uncha...
Page 47: ...on X 45 is as follows 1 Store the current PSD The stored condition code is interpreted as foil ows 2 CCl CC2 CC3 CC4 Meaning o o All digits legal and overflow Illegal digit detected Load the new PSD The condition code and instruction address portions of the PSD remain at the values loaded from memory CALL INSTRUCTION TRAP The four CALL instructions CAll CAL2 CAL3 and CAL4 cause the computer to tra...
Page 48: ...robable cause of delay is provided TCC2 is set if the CPU was using the processor bus TCC3 is set if the CPU was using the memory bus or TCC4 is set if the CPU was using the DIO bus If the instruction is not completed by the time the watchdog timer has advanced through phase 2 the instruction is aborted TCCl is set to 0 and a trap occurs immediately to Homespace location X 461 In addition TCC2 TCC...
Page 49: ...or is found this fault occurs The CPU aborts the memory request traps to Homespace location X 4C and sets TCC2 to 1 2 Data Bus Check If the CPU detects a parity error on data received from memory and the memory does not also indicate a parity error on the information sent a data bus check occurs The data bus check causes the CPU to trap to Homespace location X 4C and sets TCC3 to 1 3 Memory Parity...
Page 50: ... 1 4 cause the Reg ister AI tered bi t to be set only if the instruction requires these condition code bits as subsequent inputs Traps caused by conditions detected during operand fetch and store memory cycles such as nonexistent memory access protection violation and memory parity error may or may not leave registers memory and PsD unchanged depending on when they occur during instruction execu t...
Page 51: ... any traps occur during execution e g because of parity errors the instruction is aborted indicating in the registers at which point In general memory will be altered and the Register Altered bit set If a trap occurs the instruction will be aborted before altering registers ec1 4 may be changed but not used as input to any of these instructions If a trap occurs due to storing the old PSD or fetchi...
Page 52: ...l registers d Doubleword index al ignment the reference ad dress field of the instruction plus the displacement value can be used to address any doubleword in main memory or in the current block of general registers The addressed doubleword is auto matically located within doubleword storage boundaries e Immediate operand the instruction word contains an operand value used as part of the instructi...
Page 53: ...ementll In the execution of the instruction this field is used to modify the source address of an operand the destination address of a result or both h Ignored fields In the instruction format diagrams any area that is shaded represents a fi eld or bit position that is ignored by the computer i e the content of the shaded field or bit has no effect on instruction execution but should be coded with...
Page 54: ...These examples are intended onl y to show how the in structions operate and not to demonstrate their full capability Within the examples hexadecimal nota tion is used to represent the contents of general registers and storage locations Condition code settings are shown in binary notation The character X is used to indicate irrelevant or ignored information LOAD STORE INSTRUCTIONS The following loa...
Page 55: ...12 of the inst ruction word 12 bit positions to the left and then loads the 32 bit resul t into register R Affected R CC3 CC4 I 12 31 SE R Condi ti on code setti ngs 2 3 4 ResuItin R o 0 Zero o Negative o Positive If LI is indirectly addressed it is treated as a nonexistent instruction in which case the computer unconditionally aborts execution of the instruction at the time of opera ti on code de...
Page 56: ...x alignment I 5A R X Reference address i 48 Load Stare Instructions LOAD COMPLEMENT HALFWORD extends the sign of the effective halfword 16 bit positions to the left and then loads the 32 bit two s complement of the result into register R Overflow cannot occur Affected R CC3 CC4 EHSE R Condition code settings 2 3 4 Resul t in R 0 0 Zero 0 Negative 0 Positive LAH LOAD ABSOLUTE HALFWORD Halfword inde...
Page 57: ...MPLEMENT DOUBLEWORD forms the 64 bit two s complement of the effective doubleword loads the 32 low order bits of the result into register Ru 1 and then loads the 32 high order bits of the resul t into register R If R is an odd value the result in register R is the 32 high order bits of the two s complemented doubl eword The con dition code settings are based on the two s complement of the effectiv...
Page 58: ...int arithmetic trap mask AM is a 1 the computer traps to Homespace location X 43 after execution of LOAD ABSOLUTE DOUBLEWORD otherwise the computer executes the next instruction in sequence Example 1 even R field val ue Before execution After execution ED X 0123456789ABCDEF X O 123456789ABCD EF R xxxxxxxx X 01234567 Rul xxxxxxxx X 89ABCDEF i CC xxxx x010 50 Load Store Instructions Example 2 even R...
Page 59: ...tatus and or to perform diagnostic action on a memory bank The effective address is used to determine the mem ory bank The condition code setting immediately before execution determines the diagnostic action to be performed The effective address always references memory even if it is less than 16 The condition code can be set to the de sired value before execution of LMS with the LCF or LCFI instr...
Page 60: ...from memory CC2 Data Bus Check from CPU CC3 Parity Bit from memory CC4 0 tp 1 f d rlmar y 0 lagnostlc concern 52 Load Store Instructions Field Memory fault types Subsequent faul ts Last parity bit written Bank number Port number Tabl e 7 Status Word 0 Bits Comments 0 Reserved 1 Data parity error detected on read 2 Data parity error detected on partial write 3 Address bus parity error 4 Data bus pa...
Page 61: ... Table 8 Status Word 1 cont Field Bits Comments Unit size 8 9 8 9 0 0 8K 0 1 16K 1 0 32K 1 1 Reserved I 10 13 i Reserved i Clock margin 14 Clock margin 0 early write half cycle 15 Clock margin 1 half cycle 16 Clock margin 2 strobe 17 Clock margin 3 strobe 18 31 Reserved Table 9 Status Word 2 Field Bits Comments 0 9 Reserved Interl eaved 10 31 address of fault LS LOAD SELECTIVE Word index al ignmen...
Page 62: ...et with LCF or LCFI An initial value of 0000 for the condition code causes 16 consecutive words to be loaded into the register block Affected R to R CC 1 EWL R EWL CC l R CC l The LM instruction may cause a trap if its operation ex tends into a page of memory tha tis protected by the access protection codes A trap maya Iso occur if the operation extends into a nonexistent memory region In either c...
Page 63: ... FZ FN If 1 10 1 EB O _ 3 CC If I 10 0 CC not affected If 1 11 1 EB 5 _ 7 FS FZ FN If I 11 0 FS FZ FN not affected Condition code settings if I 10 1 2 3 4 EB 1 XW EXCHANGE WORD Word index al ignment EXCHANGE WORD exchanges the contents of register R with the contents of the effective word location Affected R EWL CC3 CC4 R EWL Condition code settings 2 3 4 Result in R 0 0 Zero 0 Negative 0 Positive...
Page 64: ...value Before execution R XI 123456781 Ru 1 X FOFOFOFO EW xxxxxxxx Example 2 odd R field value R EW STM Before execution X OOFFOOFF X 12345678 STORE MULTIPLE Word index al ignment After execution XI 123456781 X FOFOFOFO XI lx3x5x7x After executi on X OOFFOOFF STORE MULTIPLE stores the contents of a sequential set of registers into a sequential set of word locations Hie set of locations begins with ...
Page 65: ...ed at the time of trap entry The interpreting program will then know what type of violation it is trying to analyze The address that resul ts can be examined in Iight of t e originating trap If no trap condition occurs ANLZ will execute normally and return the effective address of the instruction analyzed Table 10 shows how SIGMA 9 operation codes will be inter preted by ANLZ The detailed operatio...
Page 66: ... bits 16 31 of the effective word into bit positions 16 31 of register R and loads O s into bit positions 0 15 of register R bits 4 15 of the effective word are ignored in th is case Affected R Rul CC EW O _ 3 CC EW4 15 R20 31 0 RO 19 EW 16 _ 31 Ru1 16 _ 31 0 Ru1 0 _ 15 tNote that for real or virtual addressing byte displacement is 19 bits halfword displacement is 18 bits word displace ment is 17 ...
Page 67: ...ero the result in the specified general register s is all zeros o 2 3 4 Result o Negative the instruction has produced a fixed point negative resul t o Positive the instruction has produced a fixed point positive result o Fixed point overflow has not occurred during execution of an add subtract or divide in struction and the result is correct Fixed point overflow has occurred during execution of a...
Page 68: ...ex al ignment ADD WORD adds the effective word to the contents of reg siter R and loads the sum into register R Affected R CC R EW R Trap Fixed point overflow 60 Fixed Point Arithmetic Instructions Condition code settings 2 3 4 Resu It in R o 0 Zero o Negative o Positive o No fixed point overflow Fixed point overflow o No carry from bit position 0 Carry from bit position 0 If CC2 is set to 1 and t...
Page 69: ...e two1s complement of the effec tive word adds that complement to the contents of regis ter R and loads the sum into register R Affected R CC EW R R Trap Fixed point overflow Condition code settings 2 3 4 Resul t in R o 0 Zero o Negative o Positive o No fixed point overflow Fixed point overflow o No carry from bit position 0 Carry from bit position 0 If CC2 is set to 1 and the fixed point arithmet...
Page 70: ...roduct o 0 Zero o Negative o Positive o Result is correct as represented in regis ter Rul Result is not correctly representable in reg ister Ru 1 alone If MI is indirectly addressed it is treated as a nonexistent instruction in which case the computer unconditionally aborts execution of the instruction at the time of opera tion code decoding and traps to Homespace location X 40 with the contents o...
Page 71: ...R EH R Condition code settings 2 3 4 ResuItin R Trap Fixed point overflow o 0 0 Zero quotient no overflow o 0 Negative quotient no overflow o 0 Positive quotient no overflow Fixed point overflow If CC2 is set to 1 and the fixed point arithmetic trap mask AM is a 1 the computer traps to Homespace location X 431 with the contents of register R CC1 CC3 and CC4 unchanged OW DIVIDE WORD Word index al i...
Page 72: ... the effective byte location and the condition code is set according to the value of the resultant byte This process allows modification of a byte by any number in the range 8 through 7 followed by a test If the value of the R field is zero the effective byte is tested for being a zero or nonzero value The condition code is set according to the result of the test but the effective byte is not affe...
Page 73: ...e sum is stored in the effective word location and the con dition code is set according to the value of the resultant tOther than counter 4 which uses the current active addressing mode real real extended or virtual word The sum is stored regardless of whether or not over flow occurs This process allows modification of a word by any number in the range 8 through 7 followed by a test If the value o...
Page 74: ...ion of the instruction at the time of operation code decoding and then traps to Homespace location X 40 with the condition code unchanged CB COMPARE BYTE Byte index alignment R X 9 10 II 12 1 3 66 Comparison Instructions COMPARE BYTE compares the contents of bit positions 24 31 of register R with the effective byte with both bytes treated as positive integer magnitudes and sets the condi tion code...
Page 75: ... R with the effective word in only those bit positions selected by a 1 in corresponding bit positions of register Ru 1 mask The contents of register Rand the effective word are ignored in those bit positions designated by a 0 in corresponding bit positions of register Ru 1 The selected contents of register R and the effective word are treated as positive integer magnitudes and the condition code i...
Page 76: ...fective word are both 0 a 0 remains in register R otherwise a 1 is placed in the corresponding bit position of register R The effective word is not affected 68 Logical Instructions Affected R CC3 CC4 R u EW R where 0 u 0 0 0 u 1 1 1 u 0 1 1 u 1 1 Condition code settings 2 3 4 ResuItin R EOR H o 1 2 o 0 Zero OBit 0 of register R is a 1 OBit 0 of register R is a 0 and bit positions 1 31 of register ...
Page 77: ...hmetic doubl e register 0 Searching single register Searching double register Bit positions 25 through 31 of the effective virtual address are a shift count that determines the direction and amount of the shift The shift count C is treated as a 7 bit signed binary integer with the high order bit bit posi tion 25 as the sign negative integers are represented in two s complement form A positive shif...
Page 78: ... C is negative the contents of register Rare shifted right Ici places with the contents of bit position a copied into vacated bit positions on the left Bits shifted past R31 are lost Affected R CCl CC2 Arithmetic Shift Double Register If the shift count C is positive the contents of registers R and Ru 1 are shifted left C places with OIS copied into va cated bit positions on the right Bits shifted...
Page 79: ...gn and the characteristic of the original number 3 If the fraction is not normalized the fraction field is shifted 1 hexadecimal digit position 4 bit positions to the left and the characteristic field is decremented by 1 Vacated digit positions at the right of the frac tion are filled with hexadecimal Dis If the characteristic field underflows i e is all 1 s as the result of being decremented CC2 ...
Page 80: ...it position of regis ter Ru 1 The 32 words of the conversion table are con sidered to be 32 bit positive quantities and are referred to as conversion values The intermediate results of these instructions are accumulated in internol CPU registers unti I the instruction is completed the result is then loaded into the appropriate general register Both instructions use a counter n that is set to aat t...
Page 81: ...ion code settings 2 3 4 ResuItin Ru 1 0 0 Zero OBit 0 of register Ru 1 is a 1 OBit 0 of register Ru 1 is a 0 and bit posi tion s 1 31 of register Ru1 contain at least one 1 FLOATING POINT ARITHMETIC INSTRUCTIONS The following floating point arithmetic instructions are available to SIGMA 9 computers Instruction Name Mnemonic Floating Add Short FAS Floating Add Long FAL Floating Subtract Short FSS F...
Page 82: ...x Table 11 contains examples of floating point numbers Modes of Operation SIGMA 9 contains three mode control bits that are used to qualify floating point operations These mode control bits Table 11 Floating Point Number Representation Short Floating Point Format Decimal Number C F Hexadecimal Value 16 63 1_2 24 a 111 1111 1111 1111 1111 1111 1111 1111 7F FFFFFF 16 3 5 16 a 100 0011 0101 0000 0000...
Page 83: ...normal ized form because of the characteristic being reduced below zero underflow has occurred in which case the result is set equal to true zero and the condition code is set to 1100 Exception if a trap results from significance checking with FS 1 and FZ 0 an under flow generated in the process of postnormal izing is ignored FZ 1 Characteristic underflow causes the computer to trap to Homespace l...
Page 84: ...44 with the general registers unchanged and the condition code set to 0110 if the result is positive or to 0101 if the result is negative CONDITION CODES FOR FLOATING POINT INSTRUCTIONS The condition code settings for floating point instructions are summarized in Table 12 The following provisions apply to all floating point instructions 1 Underflow and overflow detection apply to the final charact...
Page 85: ... s complement of the effective word and then operates identically to FLOATING ADD SHORT FAS If no floating point arithmetic fault occurs the difference is loaded into reg ister R as a short format floating point number Affected R cc R EW R Trap Floating point arith metic fault FSL FLOATING SUBTRACT LONG Doubleword index alignment The effective doubleword and the contents of registers R and Ru1 are...
Page 86: ...ng point arith metic fault instruc tion exception The R field of the FDL instruction must be an even va lue for proper operation of the instruction if the R field of FDL is an odd value the instruction traps to Homespace location X 4D I instruction exception trap 78 Decimal Instructions DECIMAL INSTRUCTIONS The following instructions comprise the decimal instruction sett Instruction Name Decimal L...
Page 87: ...the effective decimal operand is checked for illegal digits or signs as above However the operand in the decimal accumulator is checked to verify that there is at least one legal decimal sign code somewhere in the num ber This type of check is a result of the interruptibility of these instructions which may leave the decimal accumu lator with a partially completed result containing an internal cod...
Page 88: ...he four low order bit positions the remainder of the decimal accumulator con ta ins a II O s Negative the decimal accumulator con tains a negative decimal sign code in the four low order bit positions the remainder of the decimal accumulator contains at least one nonzero decimal digit Positive the decimal accumulator contains a positive decimal sign code in the four low order bit positions the rem...
Page 89: ...settings 2 3 4 Result in DECA 0 Illegal digit or sign detected Instruction aborted 0 Overflow 0 0 0 0 Zero No illegal digit or sign 0 0 0 Negative detected no overflow instruction completed 0 0 0 Positive OM DECIMAL MULTIPLY Byte index alignment continue after interrupt o 1 2 If no illegal digit or sign is detected in the effective deci mal operand and there is at least one decimal sign in the dec...
Page 90: ...an erroneous resul t provided that the contents of the decimal accumulator are not al tered between interrup tion and continuation Actua y the instruction is reexecuted but since there is no initializing phase it begins with the same iteration that was started prior to the interrupt 82 Decimal Instructions Affected DECA CC Trap Decimal arithmetic DECA 7 EDO DECA Condition code settings 2 3 4 Resul...
Page 91: ...it or sign detected instruction aborted o 0 0 Zero 0 0 Negative o 0 Positive o 0 Right shift or no non zero digit shifted out of DECA on left shift o PACK One or more nonzero digit s shifted out of DECA on left shift PACK DECIMAL DIG ITS No illegal digit or sign detected instruction completed Byte index alignment continue after interrupt PACK DECIMAL DIGITS converts the effective decimal operand a...
Page 92: ...OOOOOOOO 00000001 23456789 0123456D xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxx xxxx 84 Byte String Instructions No illegal digit or sign detected instruction completed After execution X OOOOOOOO 00000001 23456789 0123456D X FOFOFOF1 F2F3F4F5 F6F7F8F9 FOF1F2F3 F4F5D6 OOxx Example 2 L 8 Before execution DECA X OOOOOOOO 23000000 10001234 0012345C EDO xxxxxxxx xxxxxxxx xxxxxxxx xxxxxx CC xxxx Example ...
Page 93: ...ons 8 12 should be coded with zeros for real and virtual addressing Since the value Ru 1 is obtained by performing a logical inclusive OR with the value 0001 and the value of the R field of the instruction word the two control registers are Rand R 1 if R is even However if R is an odd value register R contains an address value that functions both as a source operand address and as a destination op...
Page 94: ...te string Thus if a destination byte string of C bytes begins with the kth byte of a source byte string numbering from 1 the first tFor real extended addressing mode this is a 24 bit field bits 8 31 for real and virtual addressing modes it is a 19 bit field 13 31 86 Byte String Instructions k 1 bytes of the source byte string are dupl icated in the destination byte string x number of times where x...
Page 95: ... location X 40 with the contents of register Rand the destination byte string unchanged See Traps By Byte String Instructions in this section for other trap conditions tFor real extended addressing mode this is a 24 bit field bits 8 31 for real and virtual addressing modes it s a 19 bit field 13 31 Case I even nonzero R field Ru1 R l Contents of register R Contents of register R 1 The source byte ...
Page 96: ...E STRING the instruction traps with the contents of register R unchanged when an odd numbered general register is speci fied by the R field of the instruction word Case III zero R field Ru 1 1 Contents of register 1 Destination address t 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 The destination byte string begins with the byte location pointed to by the destination address ...
Page 97: ...cation pointed to by the displacement in TTBS In this case the instruction automatically provides a mask of eight l s This is an exception to the general rule used in the other byte string instructions that reg ister 0 provides all O s as its contents EBS EDIT BYTE STRING Immediate displacement continue after interrupt EDIT BYTE STRING converts a decimal information field from packed decimal forma...
Page 98: ...in the destination byte string or in the dec imal informa tion field Significance is indicated by any of the following a The pattern byte is X 23 fjmmediate significance start which begins significance with the current decimal digit b The pattern byte is X 21 significance start which begins significance with the following pat tern byte c The current decimal digit is nonzero which begins significan...
Page 99: ...ns significance and set CC4 to 1 None Mode 1 Store fill character in Mode 2 pattern byte location because significance starts with next pattern byte and set CC4 to 1 Conditions Action Mark Pattern byte DS X 20 Expand digit to zoned None CC4 1 format and store digit in pattern byte location Pattern byte DS CC4 0 Expand digit to zoned format store digit in pattern byte Iocation and set CC4 to 1 to s...
Page 100: ...he illegal digit or sign is encountered and traps to Homespace location X 451 with the contents of reg ister R regi ster Ru 1 reg ister 1 the destination byte string and the condition code containing the results of the last editing operation performed before the illegal digit or sign was encountered See Traps By Byte String Instructions in this section for other trap conditions Note that the check...
Page 101: ...ode is 1010 The new contents of register 1 are XI xxx01 0031 Exampl e 4 before execution The instruction word is X 63400100 The contents of register 4 are X 7B001000 The contents of register 5 are XI 190020001 The contents of the decimal information field beginning at byte location X 1100 are 06 12 50 0 01 23 4 03 5 The contents of the destination byte string beginning at byte location X 2000 are ...
Page 102: ... down instructions the space count and the word count are each tested to determine whether the instruction would cause either count field to be incremented above the upper limit of 215 1 32 767 or to be decremented below the lower limit of O If execution of the push down instruc tion would cause either count Iimit to be exceeded the computer unconditionally aborts execution of the instruc tion wit...
Page 103: ...ow full If the next opera tion on the stack is a push instruction the instruction will be aborted If the computer does not trap to Homespace location X 421 as a result of impending stack limit overflow underflow CC2 and CC4 indicate the status of the space and word counts at the termination of the push down instruction regardless of whether the space and word counts were actually modified by the i...
Page 104: ... general registers into the push down stack defined by the stack pointer doubleword located at the effective double word address of PSM The condition code is assumed to contain a count of the number of registers to be pushed into the stack An initial value of 0000 for the condition code specifies that all 16 general registers are to be pushed into the stack The registers are treated as a circular ...
Page 105: ...e 1 and the contents of the current top of stack location become the contents of this register The last register to be loaded is register R If there is a sufficient number of words in the stack to load all of the specified registers PLM operates as follows 1 Registers R ee 1 to register Rare loaded in de scending sequence beginning with the contents of the location pointed to by the current top of...
Page 106: ...acted from the cur rent space count SPD33 47 and the result becomes the new space count 3 The modifier is algebraically added to the current word count SPD49 63 and the result becomes the new word count 4 The condition code is set to reflect the new status of the new space count and new word count tFor real extended mode of addressing this is a 22 bit field 10 31 for real and virtual addressing mo...
Page 107: ...directly addressed and the branch condi tions are satisfi ed but the address of the location containing the direct address is either non existent or unavailable for read access to the program in the slave mode 2 The branch instruction is unconditional or the branch is conditional and the condition for the branch is satisfied but the effective address of the branch instruction is either nonexistent...
Page 108: ...truction tSee Branches in Real Extended Addressing Mode in the introductory description under Execute Branch Instructions 100 Execute Branch Instructions BCR BRANCH ON CONDITIONS RESET 0 Iord index alignment BRANCH ON CONDITIONS RESET forms the logical pro duct AND of the R field of the instruction word and the current condition code If the logi cal product is zero the branch condition is satisfie...
Page 109: ...roductory description under II Execute Branch InstructionsII The BAL instruction in real extended addressing will store the fu II address of the next instruction in the spec ified R register If the Extension Selector in the PSD at the time BAL is executed is equal to zero then the address stored in the specified R register will be the incremented 16 bit dis placement from positions 16 31 of the PS...
Page 110: ...cti ons Mnemonic LPSD XPSD LRP MMC WAIT RD WD If execution of any control instruction is attempted while the computer is in the slave mode i e while bit 8 of the current program status doubleword is a 1 the computer unconditionally traps to Homespace location X 40 prior to executing the instruction PROGRAM STATUS DOUBLEWORD The SIGMA 9 program status doubleword has the following structure when sto...
Page 111: ... PSD in the doubleword location addressed by the effective address of the XPSD instruction The foI Iowi ng doubl eword is then accessed from memory and loaded into the active PSD registers The XPSD instruction is used for three distinct types of operations as a normal instruction in an ongoing program as an interrupt instruction and as a trap instruction Control bits used in the XPSD instructions ...
Page 112: ...the addition of the condition code is restricted to bits 16 to 31 of the Instruction Address The Extension Selector bit 15 and Extension Address bits 42 47 will not be affected if a carry should result 104 Control Instructions status doubleword CC3 is set to 1 Then if bit position 9 of XPSD is 1 the instruction address portion of the new program status doubleword is incremented by 2 t d Memory pro...
Page 113: ...errupt inhibit 39 EI External interrupt inhibit If any or all of bits 37 38 or 39 of the second effective doubleword are OIS the corresponding bits in the current program status doubleword remain un changed if any or all of bits 37 38 or 39 of the second effective doubleword are lIs the corresponding bits in the current program status doubleword are set to lIs See IIInterrupt System II Chapter 2 f...
Page 114: ...eration of the instruction is concerned and the results of the instruction are the same whether MMC is indirectly addressed or not The R field of MMC designates an even odd pair of general registers R and Ru1 that are used to control the loading of the specified bank of memory control registers Registers R and Ru 1 are assumed to contain the following information Register R Register Ru 1 Register ...
Page 115: ...nitial word count if 13 bit format selected t For real extended mode bits 10 31 LOADING THE ACCESS PROTECTION CONTROLS The following diagrams represent the configurations of MMC register R and register Ru 1 that are required to load the access protection control s The instruction format is The contents of register Rare The contents of register Ru 1 are ACCESS PROTECTION CONTROL IMAGE The initial a...
Page 116: ... to be loaded After interrupt the MMC instruction may be resumed from the point it was 108 Control Instructions interrupted In case of an interrupt or a parity error in a control image word the MMC wi II set the Register Altered indicator bit 60 of the program status doubleword WAIT WAIT Word index al ignment privileged o 1 2 WAIT causes the CPU to cease all operations until an inter rupt activati...
Page 117: ...t inhibit bits of the PSD and the snapshot register as follows READ SENSE SWITCHES The following configuration of RD can be used to read the control panel SENSE switches If a particular SENSE switch is set the corresponding bit of the condition code is set to 1 if a SENSE switch is zero the corresponding bit of the condition code is set to 0 see SENSE in Chapter 5 In this case only the condition c...
Page 118: ... information from the CPU If the R field of WD is nonzero the 32 bit contents of register R are transmitted to the specified element on the RD vVD data lines If the R field of WD is 0 32 O s are transmitted to the specified element instead of the contents of register 0 The specified element may return information to set the condition code Bits 16 19 of the effective virtual address determine the m...
Page 119: ...s generate a desired frequency by setting and resetting the PCF fl ip flop at the appropriate rate Execution of the above configuration of WD also resets the ALARM indicator LOAD INTERRUPT INHIBITS The following configuration of WD can be used to transfer the contents of the specified R register R29 31 to the Interrupt Inhibit field PSD 37 _ 39 Affected PSD 37 _ 39 R 29 31 PSD 37 _ 39 LOAD SNAPSHO...
Page 120: ...bit for the highest priority lowest numbered interrupt level within the group and bit position 31 of register R con tains the selection bit for the lowest priority highest numbered interrupt level within the group Each interrupt level in the designated group is operated on according to the function code specified by bits 21 through 23 of the effective address of WD The codes and their associated f...
Page 121: ...rs may have the same address 2 The four highest addresses X I1C X lFI are reserved for addressing CPUs in a multiprocessor system 3 The remaining 28 addresses may be assigned to MIOPs High Speed RAD lOPs or to any other lOP that is compatible with the SIGMA 9 computer system a SIGMA 9 MIOPs require an even odd pair of addresses The even address bit 23 is 0 selects Channel A and the odd address bit...
Page 122: ...s After the addressed device has received an order this field contains the 21 high order bits of the main memory address for the command doubleword currently being processed for the addressed device Status The meaning of this field depends on the particular I O instruction being executed and upon the selected I O device see Table 13 Byte Count After the addressed device has received an order this ...
Page 123: ... device automatic device unusual end devi ce controll er ready device controller not operational device controller unavailable device controller busy reserved incorrect length transmission data error transmission memory error memory address error lOP memory error lOP control error lOP halt High speed RIOP busy Significance for AIO data overrun unique to the device and the device controller incorre...
Page 124: ... 11 31 Control Check Fault This bit is set to 1 when a parity error occurs during a subchannel opera tion within the lOP AI ways set to O Always set to O Contain the current command doubleword address decremented by one This address is currently stored in the lOP Register R if R field is odd or register Ru 1 if Rfield is even and nonzero Status Response Bits see Tabl e 13 Bit Positi on Function a ...
Page 125: ... function of the particular device see the ap plicable peripheral reference manual Device Controller Condition If bits 5 and 6 are 00 device controller readyll all device controller conditions required for its proper operation are satisfied If bits 5 and 6 are 01 device controller IInot operational some condition has developed that does not allow it to operate properly In either case operator inte...
Page 126: ...usy high speed RIOP or an MIOP operating in the burst mode No status information is returned to general registers 118 Input Output Instructions 2 3 4 Result of no a Not possible a I O address not recognized and no status in formation is returned to general registers I O address not recognized and no status in formation is returned to general registers be cause a memory parity error or a bus check ...
Page 127: ... HALT INPUT OUTPUT causes the addressed device to im mediately halt its current operation perhaps improperly in the case of magnetic tape units when the device is forced to stop at other than an interrecord gap If the device is in an interrupt pending condition the condition is cleared If the R field of the HIO instruction is 0 or if no I O ad dress recognition exists no general registers are affe...
Page 128: ... I O address not recognized POLP POLL PROCESSOR Word index alignment privileged t See footnote to HIO instruction 120 Input Output Instructions POLL PROCESSOR causes the addressed processor to return processor fault status in bits 24 to 29 of register R In addi tion to the operation code of X 4F bits 15 16 and 17 must be coded as 010 respectively Affected R CC1 CC2 CC3 Condition code settings are ...
Page 129: ...ewords see Chapter 4 Status Response Bits see Table 13 Bit Position Function o Data Overrun 1 7 These bits are unique to the device 8 Incorrect Length As defined for SIO above 9 10 11 12 13 18 19 23 24 31 Transmission Data Error As defined for SIO above Zero Byte Count Interrupt This bit is set to 1 if the interrupt on zero byte count flag is 1 and zero byte count is detected Channel End Interrupt...
Page 130: ...o cards in a file are to be stored in specific regions of memory the I O command Iist might appear as follows 1 Read card store columns 1 10 data chain 2 Store columns 11 60 data chain 3 Store columns 61 80 command chain 122 Input Output Operations 4 Read card store columns 1 40 data chain 5 Store col umns 41 80 The SIGMA 9 CPU plays a minor rol e in the execution of an I O operation The CPU execu...
Page 131: ...ng is specified Channel end occurs when the device has transmitted all information associated with the input operation and no longer requires the use of lOP facilities for the operation Control The Control order is used to initiate special oper ations by certain devices For magnetic tape it is used to issue orders such as Rewind Backspace Record Backspace File etc Most orders can be specified by t...
Page 132: ...CE Interrupt at channel end If this flag is 1 the lOP requests the I O interrupt location XI 5C to be tri ggered when channel end occurs for the operation being controlled by this command 124 Operational Command Doubleword Bit Position 35 ICE cont Function doubleword An AIO instruction executed after the interrupt is acknowledged results in a 1 in bit position 11 of register R status information t...
Page 133: ... provide control information for the lOP The Transfer in Channel command doubleword has the foil owi ng format Transfer in Channel The Transfer in Channel command is executed within the lOP and has no direct effect on any of the I O system elements external to the addressed lOP The primary purpose of this command is to permit branching within the command Iist so that the lOP can for example repeat...
Page 134: ...n halts further servicing of this command list 126 Control Command DoubJeword The Stop command doubJeword has the following formats Stop The Stop command causes certain devices to stop generate a channel end condition and also request the I O interrupt location X 5C to be triggered if bit 0 in the Stop command is a 1 An Ala instruction executed afterthe interrupt is acknowledged results in a 1 in ...
Page 135: ...ft hand corner and labeled MPCU LOCAL NORM LOCAL MAINTI is a control mode selector for the PCP It is set either to the LOCAL NORM position for normal operations or to the LOCAL MAINT position for maintenance operations The MPCU position is reserved for future use Hereafterl this switch will be referred to as the Control Mode switch CONTROL MODE When the Control Mode switch is in the LOCAL MAINT po...
Page 136: ...be performed before using this switch Detailed loading operation is described in the section Ii Loadi ng Operation 128 Processor Contro I Pane I UNIT ADDRESS Four UNIT ADDRESS switches select the peripheral unit to be used in the loading process The two switches on the left designate an input output processor lOP The left most switch has two positions numbered 0 and 1 The next switch has 16 positi...
Page 137: ...display consists of the indicators shown in Table 14 Table 14 Program Status Doubleword PSD Indicators PSD PSD Bit PSD Portion Indicator Function Position Designation PSW2 WRITE KEY Write key status 34 35 WK INTRPT INHIB Interrupt inhibits status CI Counter interrupt group inhibit 37 CI II Input output interrupt group inhibit 38 II EI External interrupt inhibit 39 EI MA Mode a Itered 40 MA EXT ADD...
Page 138: ...rocesso r Contro I Pane I 15 ES 16 31 D pressed a single pulse is transmitted to the interrupt level advancing it to the waiting state The INTERRUPT indica tor is lighted when the control panel interrupt level is in the waiting state and it remains lighted until the interrupt level advances to the active state at which time the INTERRUPT indicator is turned off If the control panel interrupt level...
Page 139: ...elect the location to be altered 3 The DISPLAY switch to select the word to be displayed 4 The SCAN MODE switches to establish an upper bound ary of the memory scan operation 5 The SCAN START ADDR switch to enter a starting address of the memory scan operation Each SELECT ADDRESS switch represents a 1 in the upper position or a 0 in the lower position DISPLAY SWITCH The DISPLAY switch displays the...
Page 140: ...d a 3 position FORMAT SEL switch which sel ects various internal registers of the CPU for display 132 Processor Contro I Pane I FORMAT SEL The 3 position FORMAT SEL format select switch is labeled CONTROL NORMAL REGISTER In the NORMALposition the DISPLAY FORMAT and FORMAT SEL features are inac tive and the DISPLAY lights show the CPU internal instruc tion register When the FORMAT SEL switch is in ...
Page 141: ... values by manually setting the CLOCK MARGIN switch or by programming via an appropriate internal WRITE DIRECT instruction The CLOCK MARGIN switch overrides program control when set to the FAST or SLOW position When set to the NORMAL posi tion clock margins are under program control The NOT NORM CLOCK indicator will be lighted whenever the clock frequency is not normal due to programming or switch...
Page 142: ... switch to the CONT position 134 Maintenance Controls OVERRIDE MODE The OVERRIDE MODE portion of the control panel consists of the W D TIMER switch and the DECIMAL switch W D TIMER When the W D TIMER watchdog timer switch is in the NORM position the watchdog timer is operative when the switch is in the OVERRIDE position the watchdog timer is inactive DECIMAL When the DECIMAL switch is in the OVERR...
Page 143: ...ECT ADDRESS switches into an internal CPU register P which designates the starting address of the scan SCAN The SCAN indicator is on during memory scan operations initiated by the MODE switch or the MEMORY CLEAR switch EXT 010 The EXT DIO external direct input output switch controls the DIO interface directly from the PCP switches This switch is active only when the COMPUTE switch is in the IDLE p...
Page 144: ...ord for the selected device This command doubleword contains an order that instructs th e selected peripheral device to read 88 X 58 bytes into consecutive memory locations starting at word location X 2A byte location X A8 At the completion of the read operation neither data chaining nor command chaining is called for in the I O command doubleword Also the Suppress Incorrect Length flag is set to ...
Page 145: ...the DISPLAY indicators To fetch and display data from successive memory locations 1 Set COMPUTE switch to IDLE 2 Set DATA switches to desired address 3 Depress INSERT switch to PSW1 4 Depress DISPLAY switch to INSTR ADDR Contents of first memory location will be displayed in the DISPLAY indicators 5 Depress INSTR ADDR switch to INCRM Contents of successive memory locations wi II be dis played in t...
Page 146: ...types of code are shown 1 the 8 bit XDS Standard Computer Code i e the XDS Extended Binary Coded Decimal Interchange Code EBCDIC 2 the 7 bit United States of America Standard Code for Information Inter change USASCII and 3 the XDS standard card code 138 Appendix A XDS STANDARD CHARACTER SETS 1 EBCDIC 57 character set uppercase letters numerals space and I I 63 character set same as above pi us rJ ...
Page 147: ...racter EBCDIC sets These characters are included only in the XDS standard 89 character EBCDIC set XDS STANDARD 7 BIT COMMUNICATION CODES USASCII 1 Most Significant Digits NOTES O I 2 3 xOOO xOOl xOIO x011 NUL DLE SP 0 SOH DCI 5 I STX DC2 II 2 ETX DC3 3 I EOT DC4 4 ENQ NAK 5 ACK SYN 6 BEL I ETB I 7 I BS ICAN I 8 I I HT i EM 9 LF NL I SUB I VT TESC I FF i FS I CR I I GS i SO I RS I SI US i 4 5 x100 ...
Page 148: ...l 4 15 21 LF or NL 11 9 5 0 10 line feed or new line 16 22 SYN 11 9 6 1 6 sync 17 23 ETB 11 9 7 1 7 end of transmission block 18 24 CAN 11 9 8 1 8 cancel 19 25 EM 11 9 8 1 1 9 end of medium lA 26 SUB 11 9 8 2 1 10 substitute Replaces characters with parity error lB 27 ESC 11 9 8 3 1 11 escape 1C 28 FS 11 9 8 4 1 12 fj Ie separator 10 29 GS 11 9 8 5 1 13 group separator IE 30 RS 11 9 8 6 1 14 recor...
Page 149: ...10 asterisk 5D 93 11 8 5 2 9 right parenthesis 5E 94 11 8 6 3 11 semicolon 5F 95 or 11 8 7 7 14 tilde or logical not On Model 7670 is not available and USASCII 5 14 60 96 11 2 13 minus dash hyphen 61 97 0 1 2 15 slash 62 98 11 0 9 2 62 through 69 will not be assigned 63 99 11 0 9 3 64 100 11 0 9 4 65 101 11 0 9 5 66 102 11 0 9 6 67 103 11 0 9 7 68 104 11 0 9 8 69 105 0 8 1 6A 106 12 11 5 14 circum...
Page 150: ... 2 9A 154 12 11 8 2 9A through Al are unassigned 9B 155 12 11 8 3 9C 156 12 11 8 4 9D 157 12 11 8 5 9E 158 12 11 8 6 9F 159 12 11 8 7 AO 16V 11 0 8 1 Al 161 11 0 1 A2 162 s 11 0 2 7 3 A3 163 t 11 0 3 7 4 A4 164 u 11 0 4 7 5 A5 165 11 0 5 7 6 A6 166 w 11 0 6 7 7 A7 167 x 11 0 7 7 8 A8 168 Y 11 0 8 7 9 A9 169 z 11 0 9 7 10 AA 170 11 0 8 2 AA through BO are unassigned AB 171 11 0 8 3 AC In 11 0 8 4 A...
Page 151: ... DA through DF will not be assigned DB 219 12 11 9 8 3 DC 220 12 11 9 8 4 DD 221 12 11 9 8 5 DE 222 12 11 9 8 6 DF 223 12 11 9 8 7 EO 224 0 8 2 EO E1 are unassigned E1 225 11 0 9 1 E2 226 S 0 2 5 3 E3 227 T 0 3 5 4 E4 228 U 0 4 5 5 E5 229 V 0 5 5 6 E6 230 W 0 6 5 7 E7 231 X 0 7 5 8 E8 232 y 0 8 5 9 E9 233 Z 0 9 5 10 EA 234 11 0 9 8 2 EA through EF wi II not be assigned EB 235 11 0 9 8 3 EC 236 11 ...
Page 152: ... 1A 1B D DE OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C E OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E MULTIPLICATION TABLE 1 2 3 4 5 6 7 8 9 A B C D E F 2 04 06 08 OA DC DE 10 12 14 16 18 1A 1C 1E 3 06 09 DC OF 12 15 18 1B 1E 21 24 27 2A 2D 4 08 DC 10 14 18 1C 20 24 28 2C 30 34 38 3C 5 OA OF 14 19 1E 23 28 2D 32 37 3C 41 46 4B 6 DC 12 18 1E 24 2A 30 36...
Page 153: ...WERS OF TEN 2 17 E8 918 5AF3 8D7E 86F2 4578 B6B3 2304 A 64 3E8 2710 86AO F 4240 98 9680 5F5 E100 3B9A CAOO 540B E400 4876 E800 D4A5 1000 4E72 AOOO 107A 4000 A4C6 8000 6FCl 0000 5 D8A 0000 A764 0000 89E8 0000 16 o 1 0 000 000 0 0000 000 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 1999 0 28F5 004 189 0 68DB 0 A7C5 0 10C6 0 1 AD7 0 2AF3 0044B 8 0 6 DF 3 O AFE B 0 1 197 0 1 C2 5 0 2 D09 9999 C28...
Page 154: ...4680064 15728640 16 777 216 33554432 5 6 0005 0006 0021 0022 0037 0038 0053 0054 0069 0070 0085 0086 0101 0102 0117 0118 0133 0134 0149 0150 0165 0166 0181 0182 0197 0198 0213 0214 0229 0230 0245 0246 7 0007 0023 0039 0055 0071 0087 0103 0119 0135 0151 0167 0183 0199 0215 0231 0247 Hexadecimal fractions may be converted to decimal fractions as follows 1 Express the hexadecimal fraction as an integ...
Page 155: ... 0614 0615 0616 0617 0618 0619 0620 0621 0622 0623 270 0624 0625 0626 0627 0628 0629 0630 0631 0632 0633 0634 0635 0636 0637 0638 0639 280 0640 0641 0642 0643 0644 0645 0646 0647 0648 0649 0650 0651 0652 0653 0654 0655 290 0656 0657 0658 0659 0660 0661 0662 0663 0664 0665 0666 0667 0668 0669 0670 0671 2AO 0672 0673 0674 0675 0676 0677 0678 0679 0680 0681 0682 0683 0684 0685 0686 0687 2BO 0688 0689...
Page 156: ... 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 570 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 580 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 590 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 5AO 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 5BO 1456 1457...
Page 157: ...2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 870 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 880 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 890 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 8AO 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 8BO 2224 2225 ...
Page 158: ... 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 B70 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 B80 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 B90 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 BAO 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 BBO 2992 2993...
Page 159: ...3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 E70 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 E80 3712 37 13 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 E90 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 EAO 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 EBO 3760 3761...
Page 160: ... 1171875000 5E 000000 3671875000 9E 000000 6171875000 DE 000000 8671875000 1F 000000 12109 37500 5F 000000 3710937500 9F 000000 6210937500 DF 000000 8710937500 20 000000 12500 00000 60 000000 37500 00000 AO 000000 62500 00000 EO 000000 87500 00000 21 000000 12890 62500 61 000000 37890 62500 Al 000000 62890 62500 El 000000 87890 62500 22 000000 13281 25000 62 00 00 00 38281 25000 A2 000000 63281 25...
Page 161: ...005E 0000 0014343261 009E 0000 00241 08886 00 DE 0000 00338 74511 00 IF 0000 00047 30224 005F 00 00 00144 95849 009F 0000 00242 61474 00 DF 0000 00340 27099 0020 0000 00048 82812 0060 0000 00146 48437 00 AD 0000 00244 14062 00 EO 0000 00341 79687 00 21 0000 00050 35400 0061 0000 00148 01025 00 Al 0000 00245 66650 00 E1 0000 00343 32275 00 22 0000 00051 87988 0062 0000 0014953613 00 A2 0000 00247 1...
Page 162: ... 00 9E 00 00000 94175 00 00 DE 00 00001 32322 00 00 1F 00 00000 18477 00 00 5F 00 00000 56624 00 00 9F 00 00000 94771 00 00 DF 00 00001 32918 00 00 20 00 00000 19073 000060 00 00000 57220 0000 AD 00 00000 95367 0000 EO 00 00001 33514 00 00 21 00 00000 19669 00 00 61 00 0000057816 0000 Al 00 00000 95963 0000 El 00 00001 3411 0 00 00 22 00 00000 20265 000062 00 00000 58412 00 00 A2 00 00000 96559 00...
Page 163: ...0000 00218 000000 9E 00000 00367 00 00 00 DE 00000 00516 0000001F 00000 00072 00 00 005F 00000 00221 000000 9F 00000 00370 oq 00 00 DF 00000 00519 00000020 00000 00074 00000060 00000 00223 00 00 00 AO 00000 00372 0000 00 EO 00000 00521 00000021 00000 00076 00000061 00000 00225 000000 Al 00000 00374 00 00 00 E1 00000 00523 00000022 00000 00079 0000 00 62 00000 00228 000000 A2 00000 00377 00 00 00 E...
Page 164: ...4 715 202 003 717 422 485 351 562 5 140 737 488 355 328 47 0 000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25 281 474 976 710 656 48 0 000 000 000 000 003 552 713 678 800 500 929 355 621 337 890 625 562 949 953 421 312 49 0 000 000 000 000 001 776 356 839 400 250 464 677 810 668 945 312 5 1 125 899 906 842 624 50 0 000 000 000 000 000 888 178 419 700 125 232 338 905 334 472 656 25 2 ...
Page 165: ... 89 INT 6B Interpret 58 FIXED POINT ARITHMETIC PUSH DOWN AI 20 Add Immediate 59 PSW 09 Push Word 95 PLW 08 Pull Word 96 AH 50 Add Halfword 60 PSM OB Push Multiple 96 AW 30 Add Word 60 AD 10 Add Doubleword 60 PlM OA Pull Multiple 97 SH 58 Subtract Halfword 61 MSP 13 Modify Stack Pointer 98 SW 38 Subtract Word 61 SO 18 Subtract Doubleword 61 EXECUTE BRANCH MI 23 Multiply Immediate 62 MH 57 Multiply ...
Page 166: ...xed point 53 0 incl uding loads and stores Type of Instruction Percent Branch 27 5 Miscellaneous 11 0 The effect of memory interference on the above instruction mix in an 8 bank system for 100 instructions is an increase of approximately 7 4 microseconds or an average of 74 nanoseconds per instruction In a minimum SIGMA 9 con figuration a 4 bank system the effect of memory inter ference would doub...
Page 167: ...imal operand N number of nonzero decimal digits in the decimal accumulator DS 5 1 46D D number of digits including the sign in the effective decimaI operand DSA 12 5 DST 4 5 36D D number of digits including the sign to be stored DW 9 5 EBS 7 8 3 4N N number of bytes in the editing pattern EOR 73 EXU 1 2 Add execution time for subject instruction FAL 2 9 min No prealignment or postnormalization req...
Page 168: ...rocessor bus turnaround time on the interface AND 73 ANlZ 1 65 AW 73 AWM 1 77 BAl 9 BCR 81 Branch BCR 1 63 No Branch BCS 81 Branch BCS 1 63 No Branch BDR 1 10 Branch BDR 1 63 No Branch BIR 1 1 Branch BIR 1 63 No Branch CAll 4 1 98 CB 81 CBS 4 3 6N N number of destination bytes processed CD 1 4 CH 81 CI 80 ClM 1 4 ClR 92 tAdd 0 6 if analyzed instruction is indirect subtract 0 3 if it is lCFI AI LI ...
Page 169: ... postnormalization required FSL 3 35 typical One hexadecimal prealignment and one hexadecimal postnormal ization FSL 9 82 max Unnormal ized operands FSS 2 05 min No prealignment or postnormalization required FSS 2 54 typical One hexadecimal prealignment and one hexadecimal postnormal ization FSS 5 33 max Unnormal ized operands HIO 7 37 D R even f O Includes 3 flsec to claim the processor bus D tur...
Page 170: ...on bytes processed regardless of word or byte boundaries MH 2 44 MI 3 32 MMC 3 42 2 51 N L 7 map N number of words moved or 1 83N L 9 map For SIGMA 7 compatible mode use3 42 2 51N where N is the number of words Maximum N is 64 since each page is one byte For SIGMA 9 mode use 3 42 1 83N Maximum N is 128 since each page is 13 bits or approximately a halfword MSP 4 75 MTB 1 77 tAdd 0 6 if analyzed in...
Page 171: ...r of bit positions shifted S searching left 2 9 06N N number of bit positions shifted S searching right 2 7 12N N number of bit positions shifted SD 1 66 SF left 2 0 23N Single N number of hexadecimal positions shifted SF left 2 1 23N Double N number of hexadecimal positions shifted SF right 2 5 23N Single N number of hexadecimal positions shifted SF right 2 6 23N Double N number of hexadecimal po...
Page 172: ...es processed TDY 7 37 D R even 0 I Incl udes 3 fJsec to claim the processor bus I D turnaround time on the interface TDY 6 78 D R odd Includes 3 fJsec to claim the processor bus D turnaround time on the interface TDY 5 96 D R O Includes 3 fJsec to claim the processor bus D turnaround time on the interface T10 7 37 D R even 0 Incl udes 3 fJsec to claim the processor bus D turnaround time on the int...
Page 173: ...the interface TTBS 13 1 9N N number of destination bytes processed UNPK 7 1 72N N number of bytes to be stored in memory WAIT 73 Minimum time WD 1 41 Internal WD 2 07 O 24N External N integer 0 1 2 dependent on delay in external device XPSD 5 43 XW 1 77 tAdd 0 6 if analyzed instruction is indirect subtract 0 3 if it is LCFI AI LIt CBS MBS or EBS Appendix C 165 ...
Page 174: ...Status and Fault Retrieval When a fault is detected system status and fault infor mation is avai lable for program retrieval and error logging for subsequent analysis 4 Partitioning Feature 5 A SIGMA 9 system can be reconfigured through the use of reconfiguration controls SIGMA 9 units can be partitioned out of the system by selectively disabling them from the busses Thus faulty units can be isola...
Page 175: ...ring maintenance activities 3 Snapshot Logic All CPU logic that can be displayed on the PCP can be mon itored by a program with the snapshot logic At a preselected clock time of a given instruction execution selected logic is stored into a 32 bit snapshot register The contents of the snapshot register are then retrieved by a specially coded READ DIRECT instruction By com paring the snapped informa...
Page 176: ...ing during the execution of an interrupt or trap entry sequence 168 Appendix D An illegal instruction in a trap not XPSD or interrupt not XPSD MTB MTH MTW location when operating a trap or interrupt sequence The setting of the register pointer of the PSD to a nonexistent register block as a result of an LRP LPSD or XPSD An illegal MOVE MEMORY CONTROL MMC instruction An invalid register odd for an ...
Page 177: ...g of memory units is allowed on a memory port basis where each memory bus connection may se lectively be disabled Starting address switches allow the memory system to remain a contiguous unit after partitioning A centrally located reconfiguration con trol panel for each memory unit is provided for this purpose 6 Memory Mode Feature Two additional memory modes of operation are provided for testing ...
Page 178: ...ase that causes the HSRIOP to halt when entered during execution of any HSRIOP operation At this time the HSRIOP may be snapped for diagnostic purposes via RD control b Under RD control snaps one of seven selectable groups of internal HSRIOP logic c Under WD control steps the clock control of the HSRIOP in a single phase mode d Under WD control selectively sets various fault indicators e g device ...
Page 179: ...rap is in effect Term EA Meaning Extension address 6 bit field concatenated to 16 bit extended displacement field to form 22 bit real extended address EB Effective byte 8 bit contents of effective byte location EBL EBL Effective byte location byte location pointed to by effective virtual address of an instruction for byte operation ED Effective doubleword 64 bit contents of effective doubleword lo...
Page 180: ...of bits 8 11 of decimal in struction word va lue of 0 is 16 bytes 172 Appendix E Term MA MM MS PSD R RA RP Ru1 SA Meaning Mode altered bit position 40 of PSD This bit is set 1 during master protected mode of operation and during real extended type of addressing Memory map mode control bit position 9 of PSD When set 1 the memory map is in effect Master slave mode control bit position 8 of PSD When ...
Page 181: ...it bit conditions push down stack limit trap for impending overflow or underflow of space count Term TSA TW WK x X n Meaning Top of stack address pointer that points to highest numbered address of operand stack in push down instructions Trap on word inhibit bit conditions push down stack limit trap for impending overflow or underflow of word count Write key bit positions 34 and 35 of PSD they are ...
Page 182: ...LAH Load Absolute Halfword 48 20 AI Add Immediate 21 CI Compare Immediate 59 60 CBS Compare Byte String 87 22 LI Load Immediate 66 61 MBS Move Byte Stri ng 86 23 MI Multiply Immediate 47 63 EBS Edit Byte String 89 24 SF Shift Floating 62 64 BDR Branch on Decrementing Register 101 25 S Shift 71 65 BIR Branch an Incrementing Register 100 26 LAS Load and Set 69 66 AWM Add Word to Memory 64 28 CVS Con...
