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Summary of Contents for Sigma 2

Page 1: ...xrclS XDL5SIGMA 2 COMPUTER Xerox Data Systems Reference Manual...

Page 2: ...00 RIXS D 14 Load Index LDX 1100 RIXS D 14 Multiply optional MUL 0011 RIXS D 15 Register Add RADD 0111 1100 a 18 Register Add and Carry RADDC 0111 1110 a 19 Register Add and Increment RADD 0111 1101 a...

Page 3: ...00 XDS SIGMA 2 COMPUTER REFERENCE MANUAL 900964F December 1969 XJD 5 Xerox Data Systems 70l South Aviation Boulevarcl EI Segundo California 90245 1966 1967 1966 1969 Xerox Data Systems Inc Printed in...

Page 4: ...IONS Title XDS Sigma 2 3 Symbol Reference Manual XDS Sigma 2 3 Extended Symbol Reference Manual XDS Sigma 2 3 Basic FORTRAN Basic FORTRAN IV Reference Manual XDS Sigma 2 Mathematical Routines Technica...

Page 5: ...14 Hexadecimal Decimal Fraction Conversion Toble L 47 Conditional Branch Instructions 16 Table of Powers of Two 51 Copy Instruction 17 Mathematical Constants 51 Direct Control Instructions 19 B INSTR...

Page 6: ......

Page 7: ...m XDS has developed its Rapid Access Data RAD fiIes RAD units offer the large capacity and low cost of ordinary disc files In addition by using one fixed read write head for every track of data rather...

Page 8: ...put output of a full word without the use of an I O channel optional 2 General CharacterisHcs a real time priority interrupt system that features 2 to 16 internal interrupt levels and up to 132 extern...

Page 9: ...sfers to avoid tying up an automatic channel Direct I O is also useful when data is to be accepted at medium to high speeds and each input must be examined immediately when received The optional direc...

Page 10: ...e sented in two s complement form with a sign of one All arithmetic operations assume that this format is used Logi cal operations in SIGMA 2 on the other hand assume that a logical data word format c...

Page 11: ...or 20 I O chan nels The I O channel registers are loaded with control information from the accumulator by a specific configuration of the WRITEDIRECTinstruction The operation of I O channel registers...

Page 12: ...tatus indicators 7 I Accumulator I D Overflow indicator 0 Carry indicator 8L Channel 0 I III To from 9L Channel 0 I core memory Standard I O channel I Channel 3 I registers 14 To from byte I o system...

Page 13: ...is equal to the val ue in the dis placement field in the instruction plus the 16 bit value base address in index register 2 This is referred to as pre indexing or base relative addressing c If the R...

Page 14: ...r It also permits an interrupt servicing routine to defer a portion of the processing associated with an inter rupt response by processing the urgent part of the interrupt response triggering a lower...

Page 15: ...ional 267 lOB 6 11 Counter 1 0 as a set inhibited by X O 268 10C 7 12 Integral 1 Optional bit 10 of PSD 269 10D 8 13 Integral 2 as a set 270 10E 9 14 Integral 3 Optional 271 10F 10 15 Integral 4 as a...

Page 16: ...rce and cause of an I O interrupt Control Panel Interrupt Level The control panel interrupt level is connected to the INTERRUPT switch on the proces sor control panel The control panel interrupt level...

Page 17: ...its interrupt level remains in the active state Nor mally the interrupt servicing routine returns its interrupt level to the armed state and transfers program control back to the point of interrupt b...

Page 18: ...in the location whose address is contained in the dedicated interrupt location The current value in the program address P register is stored in the location following the status information The sig ni...

Page 19: ...sig nates a protected block The protection registers ccn be individually loaded by exe cuting a WRITEDIRECTinstruction with an effective address of X 8r where r is a hexadecima I digit that designates...

Page 20: ...ective location Affected El Time 5 hc 14 Instruction Repertoire LDX LOAD INDEX Displacement 8 9 10 11 12 13 14 15 LOAD INDEX loads the effective word into index 1 general reg ister 4 Affected X1 Time...

Page 21: ...reset to 0 the integer quotient is loaded into the accumulator the integer remainder is load ed into the extended accumulator and the carry indicator is set equal to the sign of the remainder The sign...

Page 22: ...during an arithmetic left shift is different from that previously in the sign bit position other wise the overflow indicator is reset to O The carry indicator is reset to 0 at the beginning of the sh...

Page 23: ...r 1 and loads the result into in dex 1 the branch condition is true only if the result in index 1 is a nonzero value The carry indicator is not affected Affected Xl P Time 4 hc branch 3 hc C I no bran...

Page 24: ...er operand is the contents of the source regi ster if the IS bit is 0 or is the inverse one s compl ement of the con tents of the source register if the ISbit is 1 18 Copy Instruc tion RCPY REGISTERCO...

Page 25: ...ion ADD based on the register operands and the final result RORC REGISTEROR AI D CARRY RORC logically inclusive ORs the source register operand with the contents of the destination register adds the c...

Page 26: ...recorded in the overflow and carry indicators Affected determined by operation Time Internal control mode except I o instructions 5 hc I O instructions and spe cial systems control mode 6 hc plus poss...

Page 27: ...nnnnnn 0 1 n n n n n n Copy bit 0 of general or I O channel register nnnnnn into the overflow indi cator and then reset bit 0 of regi ster nnnnnn to O 1 0 0 0 x x x x Copy the contents of the accumul...

Page 28: ...allation time This number is manually selected by switches within each device controller based on the equipment configura tion for the specific installation The device number not only identifies the p...

Page 29: ...ated in the Operational Status Byte or 2 The byte count reaches zero and the data chaining flag is set OPERATIONAL STATUS BYTE At the conclusi n of the I O operation the device trans mits the operatio...

Page 30: ...o initiate special operations by the device For some operations the Control order itself may be sufficient to specify the entire operation to be performed With magnetic tape operations for example the...

Page 31: ...order or even a Read or Write order that directs the device to interrupt after the trans mission operation is completed This type of interrupt gen erally occurs at device end that time during the oper...

Page 32: ...accord ing to the result of the instruction as follows a C o Significance I O address recognized and the device con troller is not busy I o address recognized and the device con troller was busy at t...

Page 33: ...ce controllers bits 1 2 and 5 6 are iden tical Some devices only differentiate between the ready and busy states rather than identifying four distinct states o Significance for TOV AIO 23456 7 unique...

Page 34: ...nd the two way access feature another SIGMA 2 CPUorspeciailydesigned 28 Direct to Memory Interface external devices may directly access core memory without CPU intervention The Direct to Memory Interf...

Page 35: ...oper ation The PHASE indicators identified with 8 4 2 and 1 are primari Iy for use by maintenance personnel PROTECT PROGR The PROTECTPROGR indicator displays the current state of the protected progra...

Page 36: ...execution of the current instruction 2 enters wait phase with the program address P regis ter pointing to the aborted instruction The wait phase is terminated by an interrupt becoming active or by mo...

Page 37: ...until the level is cleared by the control pan el interrupt servicing routine The INTERRUPTfunction is always operative The central processor performs the fol lowing operations each time the switch is...

Page 38: ...the LOAD position of the INITIALIZE switch This action clears the accumulator and the proqrom address register In addition a load condition indica tor is set within the computer and an SIO instructio...

Page 39: ...ntrol command Three types of code are shown 1 the 8 bit XDS Standard Computer Code i e the XDS Extended Binary Coded Decimal Interchange Code EBCDIC 2 the 7 bit United States of America Standard Code...

Page 40: ...in the XDS standard 89 character EBCDIC set XDS STANDARD 7 BIT COMMUNICATION CODES USASCII Most Significant Digits Decimal 0 3 4 5 rows col s 1 2 6 7 J___ Binary 1 xOOO x001 xOl0 xOll xlOO xl0l xl10...

Page 41: ...4 11 9 4 1 4 device control 4 15 LFor NL 11 9 5 0 10 line feed or new line 16 SYN 11 9 6 1 6 sync 17 ET8 11 9 7 1 7 end of transmission block 18 CAN 11 9 8 1 8 cancel 19 EM 11 9 8 1 1 9 end of medium...

Page 42: ...12 0 9 3 12 0 9 4 12 0 9 5 12 0 9 6 12 0 9 7 12 0 9 8 12 8 1 12 8 2 6 0 cent or accent grave 12 8 3 2 14 period 12 8 4 3 12 less than 12 8 5 2 8 left parenthesis 12 8 6 2 11 plus 12 8 7 7 12 vertical...

Page 43: ...1 8 7 1 99 r 12 11 9 7 2 9A 12 11 8 2 9A through Al are unassigned 9B 12 11 8 3 9C 12 11 8 4 9D 12 11 8 5 9E 12 11 8 6 9F 12 11 8 7 AO 11 0 8 1 Al 11 0 1 A2 s 11 0 2 7 3 A3 t 11 0 3 7 4 A4 u 11 0 4 7...

Page 44: ...1 9 8 2 DAthrough DF will not be assigned DB 12 11 9 8 3 DC 12 11 9 8 4 DD 12 11 9 8 5 DE 12 11 9 8 6 DF 12 11 9 8 7 I _ _ EO 0 8 2 11 0 9 1 EO El are unassigned El 11 0 9 1 E2 S 0 2 5 3 E3 T 0 3 5 4...

Page 45: ...OE OF 10 11 12 13 14 15 16 17 18 19 lA lB lC E OF 10 11 12 13 14 15 16 17 18 19 lA lB lC lD F 10 11 12 13 14 15 16 17 18 19 lA lB lC lD IE MULTIPLICATION TABLE 1 2 3 4 5 6 7 8 9 A B C D E F 2 04 06 08...

Page 46: ...56843 41886 08080 14870 x 10 13 0 35527 13678 80050 09294 x 10 14 0 22204 46049 25031 30808 x 10 15 0 13877 78780 78144 56755 x 10 16 0 86736 17379 88403 54721 x 10 18 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 47: ...fractions by successively multiplying the decimal fraction by 1610 After each multiplication the integer portion is removed to form a hexadecimal fraction by building to the right of the hexadecimal p...

Page 48: ...614 0615 0616 0617 0618 0619 0620 0621 0622 0623 270 0624 0625 0626 0627 0628 0629 0630 0631 0632 0633 0634 0635 0636 0637 0638 0639 280 0640 0641 0642 0643 0644 0645 0646 0647 0648 0649 0650 0651 065...

Page 49: ...1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 570 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 580 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1...

Page 50: ...2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 870 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 880 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2...

Page 51: ...2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 B70 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 B80 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2...

Page 52: ...3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 E70 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 szu E80 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 37...

Page 53: ...00M00221 000000 9F 00000 00370 000000 DF 00000 00519 00000020 0000000074 00000060 00000 00223 000000 AO 00000 00372 000000 EO 00000 00521 00000021 00000 00076 00000061 00000 00225 000000 Al 0000000374...

Page 54: ...00 00001 32322 0000 IF 00 00000 18477 00005F 00 00000 56624 00009F 00 00000 94771 0000 DF 00 00001 32918 000020 00 00000 19073 000060 00 00000 57220 0000 AO 00 00000 95367 0000 EO 00 00001 33514 0000...

Page 55: ...3261 009E 0000 00241 08886 00 DE 0000 00338 74511 00 IF 0000 00047 30224 005F 0000 00144 95849 009F 0000 00242 61474 00 DF 0000 00340 27099 0020 0000 00048 82812 0060 0000 00146 48437 00 AO 0000 00244...

Page 56: ...171875000 5E 000000 3671875000 9E 000000 6171875000 DE 000000 86718 75000 1F 000000 1210937500 5F 000000 3710937500 9F 000000 6210937500 DF 000000 8710937500 20 000000 12500 00000 60 000000 37500 0000...

Page 57: ...0 000 014 901 161 193 847 656 25 134 217 728 27 0 000 000 007 450 580 596 923 828 125 268 435 456 28 0 000 000 003 725 290 298 461 914 062 5 536 870 912 29 0 000 000 001 862 645 149 230 957 031 25 1 0...

Page 58: ...ve or by the COMPUTE switch being moved to the IDLE position Xl Index 1 general register 4 X2 Index 2 general register 5 At the top of the diagram reference point A assume that the COMPUTE switch is i...

Page 59: ...ighest priority interrupt l e b7 i t 7c state Addressof interrupt level S SS S PP S S 11 5 10 EI S l1 0 S 14 C S 15 P _ S 1 S 2 P S H I PP O Wff yet Figure 7 SIGMA 2 Instruction Execution Diagram Appe...

Page 60: ...SIGMA 2 memory must be reserved for reading in 2K 32 bit word of the SIGMA 5 7 memory hence the limitation to 60K in SIGMA 2 memory The maximum ad dressable number of SIGMA 2 words is 64K This can 54...

Page 61: ...ect a Write Direct WD instruction within either 8 ms 128 ms or 1 024 seconds according to the switch settings The Watchdog Timer recognizes three WD instructions o Displacement o I 0 o o 34 78 11 12 D...

Page 62: ...tput condition 26 interrupts 25 number 22 order 23 24 Disarmed interrupt level 10 Loading procedure 30 M Memory bank 54 core 4 dedicated locations 10 Memory reference instructions 14 16 p E Pari ty er...

Page 63: ...RAND Register AND 18 0111 0001 0 RANDI Register AND and Increment 19 0111 0010 0 RANDC Register AND and Carry 19 0111 0100 0 ROR Register OR 18 0111 0100 RCPY Register Copy 18 0111 0101 0 RORI Registe...

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