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CV=0V generates a binary code 00000000, 
CV=5V yields 10000000, and CV=+10V gener-
ates 11111111. Similarly, when 
offset is set 
to max (for bipolar signals), an input CV=-5V 
generates a binary code 00000000, CV=0V 
yields 10000000, and CV=+5V generates 
11111111. If your signal is hotter, it will cause 
clipping in the A/D converter unless attenuat-
ed. In general, clipping is not dangerous, but 
will not yield correct binary code. Use clipping 
indicators in the 
offset slider as a guide for 
optimum range settings.

The DAC section has two range options select-
ed with the slider switch. When set to 
high, 
it can generate voltages exceeding 20Vpp. 
With DAC 
gain set to max, a single change of 
the least significant bit corresponds to 1/12V 
(one semitone in the V/oct scale). Since there 
are 255 steps, the voltage range is 21.25Vpp. 
This is only possible if negative voltages are 
allowed. For example, setting the 
offset slider 
to minimum yields 0V at the output when the 
input code is 10000000, -10.67V for 00000000, 
and +10.58V when the code is 11111111. 
There is nothing wrong with clipping when it 
is used intentionally. For example, setting the 
offset slider to max yields 0V for the input 
code of 00000000 and 10.58V for input code 
10000000. Higher binary numbers theoretical-
ly yield voltages that cannot be handled in Eu-
rorack; hence they are clipped. The LED in the 
offset slider shaft is lit whenever the range 
of -10V to +10V is exceeded. When the switch 
is set to 
low, the DAC section halves its output 
range, and the least significant bit is ignored. 

In other words, a 1/12V step corresponds to 
the input binary number changing by 2. There 
are 127 such steps, and the voltage range is 
thus 10.58Vpp which may be bipolar or unipo-
lar. For example, setting the 
offset slider to 
minimum produces 0V at the output with the 
input code 1000000x, 0000000x yields -5.33V, 
and 1111111x yields 5.25V. Setting the 
offset 
slider to max produces unipolar voltages: 0V 
for code 0000000x, +5.33V for 1000000x, and 
+10.58V for 1111111x. The obvious applica-
tion of these calibrated ranges is to produce 
pitch voltages. However, this is not the only 
use of the DAC section.

When generating audio signals with Drezno 
II, you may need a lower amplitude but full 
resolution (no ignored bits). In such a case, set 
dac range to high, and DAC gain to a mod-
erate value. It may then be necessary to adjust 
the 
offset slider for bipolar output.

PATCH EXAMPLES

• When used standalone (with a loop cable in-
stalled at the back), processing of signals and 
voltages through ADC+DAC of Drezno II causes 
only a subtle 8-bit quantization effect. Modify-
ing the binary representation creates various 
discontinuities in the transfer function, depend-
ing on which bits are affected. Some radical de-
formations of a CV or audio signal are achieved 
by cross-patching individual 
bit outputs and 
bit inputs  (fig. 7). Many interesting, complex 
signal waveforms can be obtained by applying 
this to control voltages from LFOs, envelope gen-
erators, and even sequencers.

Summary of Contents for Drezno II

Page 1: ...DREZNO binary conversion komputor ii Model of 1989 operator s manual rev 1989 2 0...

Page 2: ...semitone steps and 20Vpp 256 semitone steps To better understand the device and avoid common pitfalls we strongly advise the user to read through the entire manual before us ing the module INSTALLATI...

Page 3: ...t digit bit is the least significant For example in an 8 bit system the highest bit represents 27 128 and the lowest bit represents 20 1 Since there are eight bits and each can have only two values th...

Page 4: ...4 fig 2 drezno ii interface controls overview 1 8 4 10 3 5 11 13 7 2 6 9 12...

Page 5: ...With gain set to max a 10Vpp input signal will fit the entire range while a hotter signal might need to be attenuated depending on the desired result The A D converter is clocked internally at a very...

Page 6: ...ation signals for the bit in puts Patching any cable into any DAC binary input breaks its normalization and overrides it with the external signal However with no signals patched to the inputs the conv...

Page 7: ...es through the Leibniz data ribbon cable It is possible to connect a chain of multiple Leibniz modules connected in series or even build a complex system with data splits and loops Feeding a time vary...

Page 8: ...For example if there is an active 5V gate at input 7 and 0V at all the re maining inputs the code is 10000000 which means 128 in the decimal system This is the middle number of the 0 255 range of num...

Page 9: ...ime about380ns Therefore the digital code resulting from this conversion is not instantly available For this reason Drezno II delays the clock s rising edge by about 450ns to account for conversion ti...

Page 10: ...e range of 10V to 10V is exceeded When the switch is set to low the DAC section halves its output range and the least significant bit is ignored In other words a 1 12V step corresponds to the input bi...

Page 11: ...dual binary outputs deliver pulse waveforms that flip between 0V and 5V many times per input period depending on the level of details they represent The average frequency of each individual input is t...

Page 12: ...RIGINALLY ACQUIRED HOWEVER IN SPECIFIC CASES WE RESERVE THE RIGHT TO CHARGE FOR LABOR PARTS AND TRANSIT EXPENSES WHERE APPLICABLE RETURN POLICY THE DEVICE INTENDED FOR REPAIR OR REPLACEMENT UNDER WARR...

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