WM8778-EV1M
w
Rev 1.1, February 2004
42
Figure 26 Data Connection to the DSP Platform (+5V tolerant input levels)
The connection in Figure 26 is applicable when links J9, J11 and J14 are fitted for common
DAC and ADC MCLK, BCLK and LRC clocks. If separate ADC clocks are required then
remove links J9, J11 and J14 and connect the separate clocks as shown in Figure 27. The
ADC data can then be connected to the point relevant for the DSP power supply, either H2
(5v tolerant) or H3 (direct to device).
H2
GND
ADCMCLK
ADCLRC
ADCBCLK
GND
GND
Figure 27 Connections to DSP Platform
When the WM8778 is set to
Master mode
(DAC and ADC), the jumpers on header H1
should be removed, disconnecting the digital input section of the evaluation board. If an
external MCLK signal is being used (i.e. supplied by the DSP) then the DSP platform should
be connected as shown in Figure 28 for MCLK and DIN. The signals should be connected to
H1 and not on the header strip H3 running up the side of the device. Connecting the signals
on the output side of the level-shift IC (U5) will cause drive contention between U5 and the
DSP and could result in damage to either or both devices. In most cases, the DSP supplies
will be set around +3V for low power portable applications. The inputs to the level-shift IC
(74ALVC164245) have a TTL threshold (i.e. Logic High = +2V(min); Logic Low = +0.8V(max))
and low input current requirements (i.e. 15uA max) allowing most DSPs to connect directly.
Figure 28 Timing Connections from DSP Platform
The digital inputs to the WM8778 have a CMOS threshold (i.e. Logic High (min) = DVDDx0.7;
Logic Low (max) = DVDDx0.3). These are met directly by the level shift IC outputs.
The DACBCLK and DACLRC signals can then be connected directly to the device on header
H3 pin 4 and pin 7 respectively.
The jumpers on H2 should also be removed, disconnecting the digital output section of the
WM8778 evaluation board.
The DOUT, ADCBCLK and ADCLRC signals should be taken direct from the WM8778 digital
output as the output side of the level-shift IC (U4) from the WM8778 is pulled up to +5V
which may overdrive and cause damage to the DSP inputs. The digital output levels of the
Summary of Contents for WM8778-EV1B
Page 1: ...WM8778 EV1B Evaluation Board User Handbook Rev 1 1...
Page 25: ...WM8778 EV1M w Rev 1 1 February 2004 25 SCHEMATIC LAYOUT Figure 13 Functional Diagram...
Page 26: ...WM8778 EV1M w Rev 1 1 February 2004 26 Figure 14 Digital Input...
Page 27: ...WM8778 EV1M w Rev 1 1 February 2004 27 Figure 15 Software Control...
Page 28: ...WM8778 EV1M w Rev 1 1 February 2004 28 Figure 16 Level Shift...
Page 29: ...WM8778 EV1M w Rev 1 1 February 2004 29 Figure 17 Analogue Input and Output Mute...
Page 30: ...WM8778 EV1M w Rev 1 1 February 2004 30 Figure 18 WM8778...
Page 31: ...WM8778 EV1M w Rev 1 1 February 2004 31 Figure 19 Analogue Output...
Page 32: ...WM8778 EV1M w Rev 1 1 February 2004 32 Figure 20 Power...
Page 33: ...WM8778 EV1M w Rev 1 1 February 2004 33 WM8778 EV1B PCB LAYOUT Figure 21 Top Layer Silkscreen...
Page 34: ...WM8778 EV1M w Rev 1 1 February 2004 34 Figure 22 Top Layer...
Page 35: ...WM8778 EV1M w Rev 1 1 February 2004 35 Figure 23 Bottom Layer...
Page 36: ...WM8778 EV1M w Rev 1 1 February 2004 36 Figure 24 Bottom Layer Silkscreen...
