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PPM-C412/Configuration

v1.0

www.winsystems.com

Page 32

MODE - Selects the communication mode of the serial port (set in BIOS and should be 

maintained).

Example: 

Set COM1 to RS-485 Auto with termination and COM2 RS-422 Auto with 

SKEW:

Write 0x00 to 0x1E9

Points to COM1-2 Mode controls

Write 0x2E to 0x1EA

COM1 - 485TE, TERM2, EN1, MODE 2

Write 0x37 to 0x1EB

COM2 - 485TE, SLEW2, EN2, MODE 3

Layout and Pin Reference

Line Printer Port (LPT) 

The LPT port is a multimode parallel printer port that supports the PS/2 standard 

bidirectional parallel port (SPP), enhanced parallel port (EPP), and extended capabilities 

port (ECP) functionality. The output drivers support 8 mA per line.

The LPT interface is provided at connector 

J7

, which is an 80-pin Hirose high density 

connector. WinSystems offers the cable CBL-251-G-1-1.5 to simplify the connection. 

The pinout for the connector and cable is listed in detail in the cable drawing. This cable 

is includes in the cable set CBL-SET-412-1.

If a printer is not required, the printer port can also be used as two additional 

general-purpose I/O ports. The first port is configured as eight input or output only 

lines. The other port is configured as five input and three output lines.

Table 19: 

Modes

Mode

Description

0

LOOPBACK

1

RS232

2

RS485

3

RS422

DB-9 Female

Pin

RS-232 Interface Signal

1

Protection grounding DCD

2

Receiving data SIN (RXD)

3

Sending data SOUT (TXD)

4

Data termination preparation DTR

5

Signal grounding GND

6

Data equipment preparation DSR

7

Request sending RTS

8

Clear sending CTS

9

Ring indication RI

Summary of Contents for PPM-C412

Page 1: ...WinSystems Inc 715 Stadium Drive Arlington Texas 76011 817 274 7553 info winsystems com www winsystems com PPM C412 PC 104 Plus Single Board Computer Based on DM P Vortex DX3 CPU Product Manual...

Page 2: ...makes no warranty express statutory implied or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement WinSystems Inc make...

Page 3: ...ttom View 14 7 1 3 Top View Indicators and Jumpers 15 7 2 I O Port Map 16 7 3 Interrupt Map 18 7 4 PCI Devices and Functions 19 7 5 DOS Legacy Memory Map 20 7 6 Memory Shadowing 20 7 7 I O Address Spa...

Page 4: ...I 104 Bus 35 7 12 10 J101 SATA Serial ATA SATA 37 7 12 11 J102 Digital Input Output or GPIO 37 7 12 12 J104 LVDS Audio Connector 38 7 12 13 J105 USB 2 0 Ports 40 7 12 14 J106 Analog VGA Connector 41 7...

Page 5: ...PPM C412 v1 0 www winsystems com Page 5 10 Software Drivers 54 A Best Practices 55 B Mechanical Drawings 58 C Power on Self Test POST Codes 60 D Warranty Information 63...

Page 6: ...ts that can be used with your PPM C412 3 Functionality The PPM C412 is a single board computer SBC It is a full featured embedded system with a variety of on board I O options Two display interfaces V...

Page 7: ...S panel and VGA mode is also supported The VGA connector is located at J106 The LVDS interface is located at J104 The mode is selected in the BIOS The backlight power connector is located at J107 Cont...

Page 8: ...Four USB 2 0 ports with ESD suppression Four serial COM ports Two RS232 422 485 Two RS232 only Bus Expansion PC 104 Plus PC 104 and PCI 104 Line Printer Port Bidirectional SPP ECP EPP Watchdog Timer U...

Page 9: ...PPM C412 General Operation v1 0 www winsystems com Page 9 Activity status LEDs on board PS 2 keyboard and mouse supported 5 General Operation 5 1 System Block Diagram...

Page 10: ...terface Four USB 2 0 ports Serial interface Four serial channels with RS 232 levels plus RS 422 485 on COM1 and COM2 General purpose input output GPIO 24 bidirectional I O lines 5V tolerant with 12mA...

Page 11: ...40 to 176 F with additional heat sink still air Operational from 40 to 85 C 40 to 185 F with additional heat sink 200 LFM airflow Humidity RH 5 to 95 non condensing Mechanical shock testing MIL STD 2...

Page 12: ...ation 7 1 Component Layout The PPM C412 provides components on the top and bottom of the board 7 1 1 Top View NOTE The reference line to each component part has been drawn to Pin 1 and is also highlig...

Page 13: ...mponents Component Description Reference J1 SATA power page 24 J3 Power page 25 J4 Battery page 25 J5 PC 104 16 bit page 26 J6 PC 104 8 bit page 26 J7 Multi I O PS 2 keyboard PS 2 mouse serial ports 1...

Page 14: ...ATA J106 VGA J105 USB J102 GPIO J104 LVDS audio J100 Gigabit Ethernet LEDs J103 Gigabit Ethernet D100 Gigabit Ethernet LED Table 3 Bottom view components Component Description Reference J100 Gigabit E...

Page 15: ...roper boot when no external CMOS battery is connected D1 10 100 Ethernet speed D2 10 100 Ethernet link activity D3 CFlash activity JP1 battery D6 Status LED Table 4 Top view LEDs Component Description...

Page 16: ...05F Free 060 06F 8042 Keyboard mouse controller 070 07F CMOS RAM clock calendar 080 09F DMA page registers 0A0 0BF 8259 PIC 2 0C0 0DF 8237 DMA controller 2 0E0 0EF DOS 4G 32 bit DOS extender register...

Page 17: ...2FF COM2 default 300 377 Free 378 37B LPT default 37C 3A7 Free 3A8 3AF Free option for on board serial ports 3B0 3BB Video controllers 3BC 3BF Free option for LPT 3C0 3DF Video controllers 3E0 3E7 Fre...

Page 18: ...ble 7 IRQ resources IRQ Device IRQ0 18 2 Hz heartbeat IRQ1 Keyboard IRQ2 Chained to slave controller IRQ9 IRQ3 COM2 IRQ4 COM1 IRQ5 COM3 IRQ6 COM4 IRQ7 LPT IRQ8 Real time clock IRQ9 Free IRQ10 Digital...

Page 19: ...h AHCI 0F23h AHCI Device SATA 0 26 0 0F18h Device Trusted execution engine 0 27 0 0F04h Device HD audio 0 28 0 0F48h Device PCI Express Function Root port 1 1 0F4Ah Device PCI Express Function Root po...

Page 20: ...decodes accesses to all internal registers including PCI configuration registers CF8h and CFCh PC AT compatible I O registers 8237 8254 and 8259 and all relocatable I O space registers UART Table 9 Ex...

Page 21: ...flects the combined state of the INT_ID0 through INT_ID2 registers When any of the lower three bits are set it indicates that an interrupt is pending on the I O port corresponding to the bit position...

Page 22: ...is selected They are used to identify currently pending edge interrupts A bit when read as a 1 indicates that an edge of the polarity programmed into the corresponding polarity register has been reco...

Page 23: ...second to 256 minutes If port 565h bit 7 equals 0 the timeout value written into I O address 566h is in minutes The timeout value written to address 566h is in seconds if port 565 bit 7 equals 1 7 9...

Page 24: ...e clock section A battery must be enabled for the real time clock to retain time and date during a power down 7 11 SP1 Speaker An on board speaker SP1 is available for sound generation 7 12 Connectors...

Page 25: ...out or power fail conditions The reset circuit also ensures that the power is nominal before releasing reset A reset condition occurs when VCC drops between 4 6V and 4 75V for more than 150 ms Layout...

Page 26: ...BAT LTC E 36 27 1 connected to J4 simplify these connections to the board 7 12 4 J5 J6 PC104 PC 104 Bus The PC 104 bus is electrically equivalent to the 8 and 16 bit ISA bus Standard PC 104 I O cards...

Page 27: ...WS D0 GND C0 GND A9 SD0 B9 12V D1 MEMCS16 C1 SBHE A10 IOCHRDY B10 GND D2 IOCS16 C2 LA23 A11 AEN B11 SMEMW D3 IRQ10 C3 LA22 A12 SA19 B12 SMEMR D4 IRQ11 C4 LA21 A13 SA18 B13 IOW D5 IRQ12 C5 LA20 A14 SA1...

Page 28: ...ard PS 2 mouse four serial LPT ENET2 and PBReset all terminated via the connector at J7 A cable part number CBL 251 G 1 1 5 is available from WinSystems to adapt to the conventional I O connectors and...

Page 29: ...COM2 RTS A14 GND LPT B14 COM2 TX A15 PD6 LPT B15 COM2 CTS A16 GND LPT B16 COM2 DTR A17 PD7 LPT B17 COM2 RI A18 GND LPT B18 COM2 GND A19 ACK LPT B19 COM3 DCD A20 GND LPT B20 COM3 DSR A21 BUSY LPT B21 C...

Page 30: ...of each channel have a 16 byte FIFO All serial ports have 16C550 compatible UARTs Independent control of transmit receive line status and data set interrupts are on all channels Each channel is setup...

Page 31: ...able 0 RTS enable Default 1 TXD enable SLEW Limit slew rate to 250 kbps Default 0 Max data rate TERM Enables RS 422 485 terminations Default 0 Disabled EN Enables the SP339 multimode UART Default 1 En...

Page 32: ...erface is provided at connector J7 which is an 80 pin Hirose high density connector WinSystems offers the cable CBL 251 G 1 1 5 to simplify the connection The pinout for the connector and cable is lis...

Page 33: ...s detected and off if a 10Base T link is detected Ethernet activity signals are also provided at connector J7 to allow optional status LEDs to be mounted off board The Ethernet activity signals are ac...

Page 34: ...J103 network interface Layout and Pin Reference Connectors PCB connector Samtec TFM 105 02 L DH Mating connector Samtec ISDF 05 D M housing Mating connector Samtec CC03M 2830 01 G or CC03R 2830 01 G c...

Page 35: ...that provide high performance and extended temperature operation 40 to 85 C An IDE activity LED is present at D3 7 12 9 J9 PC 104 Plus PCI 104 Bus The PPM C412 supports peripheral expansion using the...

Page 36: ...RVED 11 STOP 3 3V LOCK GND 12 3 3V TRDY GND DEVSEL 13 FRAME GND IRDY 3 3V 14 GND AD16 3 3V C BE2 15 AD18 3 3V AD17 GND 16 AD21 AD20 GND AD19 17 3 3V AD23 AD22 3 3V 18 IDSEL0 GND IDSEL1 IDSEL2 19 AD24...

Page 37: ...alent Mating connector 3M 5607 4200 SH 1x7 right angle 7 12 11 J102 Digital Input Output or GPIO NOTE DIO and GPIO are synonymous digital vs general purpose input output GPIO is used for the general r...

Page 38: ...pins 1 through 21 non shaded in the following table Pin Name Pin Name 1 Port 2 Bit C7 2 GND 3 Port 2 Bit C6 4 GND 5 Port 2 Bit C5 6 GND 7 Port 2 Bit C4 8 GND 9 Port 2 Bit C3 10 GND 11 Port 2 Bit C2 12...

Page 39: ...Ampire CBL LVDSB 006 12 LVDS and backlight to 7 Ampire CBL LVDSA 007 12 LVDS and audio to 12 Mitsubishi CBL LVDSA 008 18 LVDS and audio to 12 Mitsubishi CBL LVDSAB 003 08 LVDS audio and backlight to 6...

Page 40: ...to an 20 pin Molex Pico Clasp connector at J105 Layout and Pin Reference Connectors PCB connector Molex 501571 2007 USB Pico Clasp Mating connector Molex 501189 2010 housing Mating connector Molex 50...

Page 41: ...ce Both outputs may be active simultaneously Layout and Pin Reference Connectors PCB connector Molex 87832 series 2 x 7 1 mm box header or equivalent Mating connector Molex 51110 1451 Mating connector...

Page 42: ...and backlight to 7 Ampire CBL LVDSB 006 12 LVDS and backlight to 7 Ampire CBL LVDSAB 003 18 LVDS audio and backlight to 6 5 AUO CBL LVDSAB 009 18 LVDS audio and backlight to 12 1 AUO 7 13 LED Indicato...

Page 43: ...of CMOS configuration see BIOS Setting Storage Options on page 53 Access to this setup information is via the Setup Utility in the BIOS 8 2 Entering Setup To enter setup power up the computer and pres...

Page 44: ...0 01 VBIOS Date 01 16 2015 FPGA Revision 0003 EC Support Disabled Processor Type DMP R A9126 Speed 1000MHz System Memory Size Speed System Information UUID 00020003 0004 0005 0006 000700080009 MAC1 00...

Page 45: ...ug Mode Disabled Disable Reset Function No Begin Disable Watch Dog Functi No uControl Support Disabled DRAM Refresh 15uS Keyboard Control Select Auto Advanced Chipset Settings NorthBridge Configuratio...

Page 46: ...set Settings NorthBridge Configuration DRAM Configuration DDR Setting By BIOS DDR PHY Control Setting By BIOS Enhanced RWP Policy Disabled NB Function 1 Register BC 0 NB Function 1 Register BD 0 NB Fu...

Page 47: ...et Configuration ISA Configuration ISA Clock 8 3MHz ISA 16bits I O wait state 1 clock ISA 8bits I O wait state 4 clock ISA 16bits Memory wait state 1 clock ISA 8bits Memory wait state 4 clock Advanced...

Page 48: ...nfiguration SB Serial Port 1 3F8 Serial Port IRQ 1 IRQ4 Serial Port Baud Rate 115200 BPS Serial Port 1 Mode RS232 SB Serial Port 2 2F8 Serial Port IRQ 2 IRQ3 Serial Port Baud Rate 115200 BPS Serial Po...

Page 49: ...guration Advanced Power Management Configuration APM Configuration APM Support Disabled Advanced Power Management Configuration ACPI Configuration ACPI Aware O S Yes General ACPI Configuration Advance...

Page 50: ...tion End of POST PCIPnP Advanced PCI PnP Settings Warning Setting the wrong values in these sections may cause the system to malfunction Clear NVRAM No Plug Play O S No PLI Latency Timer 64 Allocate I...

Page 51: ...ait For F1 If Error Enabled Hit DEL Message Display Enabled Interrupt 19 Capture Enabled Onboard VGA GPUP Enabled Onboard VGA GPURST Enabled VGA Share Memory 64 MB Boot Display Device CRT Beep Functio...

Page 52: ...Security Security Settings I O Interface Security USB Control 1 Interface Enabled USB Control 2 Interface Enabled USB Device Interface Disabled LAN Network Interface Enabled COM4 Port Interface Enable...

Page 53: ...dating the BIOS FLASH PROM The most recent PPM C412 BIOS is available on the WinSystems website at www winsystems com However it is highly recommended that an Applications Engineer be consulted prior...

Page 54: ...e CBL LED3 001 12 Same terminated LED extension cable CBL SPL 001 14 LVDS and audio to unterminated LVDS with audio jacks BAT LTC E 36 16 1 External 3 6V 1600 mAH battery with plug in connector BAT LT...

Page 55: ...C412 Power Down Make sure that power has been removed from the system before making or breaking any connections Avoid Electrostatic Discharge ESD Only handle the circuit board and other bare electron...

Page 56: ...nd are connected to the embedded computer module s ground plane Traces are often routed in the inner layers right below above or around the mounting holes Never use a drill or any other tool in an att...

Page 57: ...ct warranty if it is properly removed prior to return Coating may change thermal characteristics and impedes our ability to test diagnose and repair products Any coated product sent to WinSystems for...

Page 58: ...PPM C412 Mechanical Drawings v1 0 www winsystems com Page 58 Appendix B Mechanical Drawings PPM C412 Drawing Top and Side Views PPM C412 Drawing Bottom View...

Page 59: ...PPM C412 Mechanical Drawings v1 0 www winsystems com Page 59...

Page 60: ...zed CMOS as mentioned in the kernel variable wCMOSFlags 04 Checks CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK Verifies CMOS checksum manually by reading storage ar...

Page 61: ...int 39 Initializes DMAC 1 and DMAC 2 3A Initializes RTC date time 3B Tests for total memory installed in the system Checks for DEL or ESC keys to limit memory test Displays total memory in the system...

Page 62: ...odule Displays boot option popup menu A7 Displays the system configuration screen if enabled Initializes the CPUs before boot which includes the programming of the MTRRs A9 Waits for user input at con...

Page 63: ...ty WinSystems shall pay freight and insurance charges for any repaired or replaced Products or Software thereafter delivered to Customer within the United States All fees and costs for shipment outsid...

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