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Vizio L37, Service Manual

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Vizio L37 Service Manual Download Page 29

CONFIDENTIAL – DO NOT COPY

 

Page 6-

1

 

File No. SG-0176

 

Chapter 6   Block Diagram 

The TV system block diagram is powered by power board that transforms AC source 
of 100V~240V AC +/- 10% @ 50/60 HZ into DC 5V & 12V& 24Vsource. The main 
board receives different types of video signal into the MTK8205 Ic. Afterward, the 
MTK8205 Ic process the signals control the various functions of the monitor and 
outputs control signal, video signal and power to the 37” WXGA panel to be 
displayed.  
The power send to the panel is first processed by the inverter.   

Summary of Contents for L37

Page 1: ...Service Manual V Inc 320A Kalmus Drive Costa Mesa CA 92626 TEL 714 668 0588 FAX 714 668 9099 Top Confidential Model VIZIO L37 ...

Page 2: ...ctory Preset Timings 4 1 5 Pin Assignment 5 1 6 Main Board I O Connections 6 1 7 Theory of Circuit Operation 7 1 8 Waveforms 8 1 9 Trouble Shooting 9 1 10 Block Diagram 10 1 11 Spare parts list 11 1 12 Complete Parts List 12 1 Appendix 1 Main Board Circuit Diagram 2 Main Board PCB Layout 3 Assembly Explosion Drawing Block Diagram ...

Page 3: ...unications However there is no guarantee that the interference will not occur in a particular installation If this equipment does cause unacceptable interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures reorient or relocate the receiving antenna inc...

Page 4: ...uto adjust function for automatic adjument of screen display 6 Smoothing function enables display of smooth texts and graphics even if image withresolution lower than 1366x768 is magnified 7 Picture In Picture PIP funtion to show TV or VCR images 8 Power saving to reduce consumption power too less than 3W 9 On Screen Display user can define display mode i e color brightness contrast sharpness soun...

Page 5: ...nt Hard coating 3H Anti glare treatment of the front polarizer Color Depth 8 bit 16 7 M colors Viewing Angle CR 10 Viewing angle free R L 176 Typ U D 176 Typ Power Consumption Total 125Watt Typ Logic 4 5W Lamp 120W IBL 6 0mA 2 OPTICAL CHARACTERISTICS Viewing Angle by Contrast Ratio Left 88 typ Right 88 typ Top 88 typ Bottom 88 typ 3 SIGNAL Refer to the Timing Chart 3 1 Input Voltage Level 90 240 V...

Page 6: ...w Video Y c Frequency H 15 734KHz V 60Hz NTSC 3 2 3 F Type TV RF connector 3 2 3 1 NTSC System a Signal Level Analog 1Vp p typical 45dB 90dB b System NTSC c Frequency 55 801MHz NTSC 3 2 3 2 ATSC System a IF output level 1Vp p minimum b System ATSC c Frequency 57 863MHz ATSC 3 2 4 PC connector 15 pin male D sub connector a Pin Assignment ...

Page 7: ...ideo R G B Analog 0 7Vp p 75 Sync H V TTL level c Sync Type TTL Separate Composite or Sync On Green d Sync polarity Positive or Negative e Frequency H support to 30K 70KHz V support to 50 85Hz Pixel Clock support to 110MHz 3 2 5 HDMI Signal Digital HD a Pin Assignment ...

Page 8: ...DENTIAL DO NOT COPY Page 2 4 File No SG 0176 b Type TYPE A c Polarity Positive or Negative d Frequency H 15 734KHz V 60Hz NTSC 480i H 31KHz V 60Hz NTSC 480p H 45KHz V 60Hz NTSC 720p H 33KHz V 60Hz NTSC 1080i ...

Page 9: ...Hz V 60Hz NTSC 720p H 33KHz V 60Hz NTSC 1080i b Signal level Y 1Vp p Pb 0 350Vp p Pr 0 350Vp p c Impedance 75 3 2 7 Audio Signal a Signal Level 1Vrms b Frequency Response 250Hz 20KHz 4 Input Connectors RJ11 D SUB15PIN mini jack PC Audio in HDMI CONNECT RCAX2 component RCAX3 AUDIO in RCAX3 composite RCAX3 AUDIO in F CONNECTx2 S Video 5 POWER SUPPLY Power Consumption 220W MAX Power OFF to less than ...

Page 10: ...and chlorine type materials for the cover case are not desirable because the former generates corrosive gas of attacking the polarizer at high temperature and the latter causes circuit break by electro chemical reaction 6 Do not touch push or rub the exposed polarizes with glass tweezers or anything harder than HB pencil lead And please do not rub with dust clothes with chemical treatment Do not t...

Page 11: ...high frequency circuits Sufficient suppression to the electromagnetic interference shall be done by system manufacturers Grounding and shielding methods may be important to minimized the interference 9 3 HANDLING PRECAUTIONS FOR PROTECTION 1 The protection film is attached to the bezel with a small masking tape When the protection film is peeled off static electricity is generated between the film...

Page 12: ...GHTNESS 0 100 d Adjust the CONTRAST 0 100 e Adjust the COLOR saturation 0 100 f Adjust the TINT hue 0 100 g Adjust the SHARPNESS 0 100 h CLOSED CAPTION OFF CC1 CC2 CC3 CC4 TT1 TT2 TT3 TT4 B AUDIO ADJUST a VOLUME 0 100 b BASS 0 100 c TREBLE 0 100 d BALANCE 0 100 e SURROUND ON OFF f REVERB OFF CONCERT LIVINGROOM HALL ARENA g MUTE ON OFF h SPEAKERS ON OFF C TV TUNER SETUP a SOUND SAP MONO STEREO b TV...

Page 13: ... LEFT MIDDLE RIGHT BOTTOM LEFT BOTTOM CENTER BOTTOM RIGHT F SPECIAL FEATURES a LANGUAGE ENGLISH FRANCE SPANISH b SLEEP TIMER OFF 30 60 90 120 c WIDE FORMAT NORMAL WIDE ZOOM PANORAMIC d RESET ALL SETTING PC Analog Mode A PICTURE ADJUST a AUTO PICTURE Run b Adjust the BACKLIGHT 0 100 c Adjust the BRIGHTNESS 0 100 d Adjust the CONTRAST 0 100 e Adjust the V POSITION 0 100 f Adjust the H SIZE 0 100 g A...

Page 14: ...TOP RIGHT MIDDLE LEFT MIDDLE RIGHT BOTTOM LEFT BOTTOM CENTER BOTTOM RIGHT E SPECIAL FEATURES a LANGUAGE ENGLISH FRANCE SPANISH b SLEEP TIMER OFF 30 60 90 120 c WIDE FORMAT WIDE NORMAL d RESET ALL SETTING DIGITAL HD MODE A PICTURE a PICTURE MODE USER VIVID1 VIVID2 VIVID3 b Adjust the BACKLIGHT 0 100 c Adjust the BRIGHTNESS 0 100 d Adjust the CONTRAST 0 100 e Adjust the COLOR saturation 0 100 f Adju...

Page 15: ...LEFT TOP CENTER TOP RIGHT MIDDLE LEFT MIDDLE RIGHT BOTTOM LEFT BOTTOM CENTER BOTTOM RIGHT E SPECIAL FEATURES a LANGUAGE ENGLISH FRANCE SPANISH b SLEEP TIMER OFF 30 60 90 120 c WIDE FORMAT NORMAL WIDE ZOOM d RESET ALL SETTING Video Sources AV1 AV2 AV3 ANALOG HD1 ANALOG HD2 A PICTURE a PICTURE MODE USER VIVID1 VIVID2 VIVID3 b Adjust the BACKLIGHT 0 100 c Adjust the BRIGHTNESS 0 100 d Adjust the CONT...

Page 16: ...RCE AV2 AV3 ANALOGHD1 ANALOG HD2 DIGITAL HD RGB TV c SIZE SMALL 20 MEDIUM 30 LARGE 40 d POSITION TOP LEFT TOP CENTER TOP RIGHT MIDDLE LEFT MIDDLE RIGHT BOTTOM LEFT BOTTOM CENTER BOTTOM RIGHT E SPECIAL FEATURES a LANGUAGE ENGLISH FRANCE SPANISH b SLEEP TIMER OFF 30 60 90 120 c WIDE FORMAT NORMAL WIDE ZOOM PANORAMIC d RESET ALL SETTING DTV Sources A PICTURE a PICTURE MODE USER VIVID1 VIVID2 VIVID3 b...

Page 17: ...T LIVING ROOM HALL ARENA g MUTE ON OFF h SPEAKERS ON OFF C DTV OSD a DTV TUNER SETUP 1 TIME ZONE α HAWALL β EASTTERN TIME γ INDIANA δ CENTRAL TIME ε MOUNTAIN TIME ζ ARIZONA η PACIFIC TIME θ ALASKA 2 AUTO SCAN 3 MANUAL SCAN PRESS OK 1 ADD ON MODE 2 RANGE MODE α FORM CHANNEL 2 69 β TO CHANNEL 2 69 4 CHANNEL SKIP PRESS OK b CLOSED CAPTION 1 ANALOG COLOSED CAPTION α OFF β CC1 γ CC2 δ CC3 ε CC4 ...

Page 18: ...E3 ε SERVICE4 ζ SERVICE5 η SERVICE6 3 DIGITAL CAPTION STYLE PRESS OK 1 AS BROADCASTER 2 CUSTOM FONT SIZE α LARGE β SMALL γ MEDIUM FONT COLOR α BLACK β WHITE γ GREEN δ BLUE ε RED ζ CYAN η YELLOW θ MAGENTA FONT OPACITY α SOLID β TRANSLUCENT γ TRANSPARENT BLACKGROUND COLOR α BLACK β WHITE γ GREEN δ BLUE ε RED ζ CYAN ...

Page 19: ...DOW OPACITY α SOLID β TRANSLUCENT γ TRANSPARENT c PARENTAL CONTROL PASSWORD PRESS OK 1 0000 2 CHANNEL BLOCK PRESS OK D PARENTAL CONTROL a PARENT LOCK ENABLE ON OFF b TV RATING c MOVIE RATING d ACCESS CODE EDIT E PIP SETUP a STYLE OFF PIP POP b SOURCE AV1 AV2 AV3 TV c SIZE SMALL 20 MEDIUM 30 LARGE 40 d POSITION TOP LEFT TOP CENTER TOP RIGHT MIDDLE LEFT MIDDLE RIGHT BOTTOM LEFT BOTTOM CENTER BOTTOM ...

Page 20: ...CONFIDENTIAL DO NOT COPY Page 3 9 File No SG 0176 F SPECIAL FEATURES a LANGUAGE ENGLISH FRANCE SPANISH b SLEEP TIMER OFF 30 60 90 120 c WIDE FORMAT NORMAL WIDE d RESET ALL SETTING ...

Page 21: ...zontal Polarity Vertical Polarity Pixel Rate 640x480 60Hz 31 5kHz 59 94Hz N N 25 175 640x480 75Hz 37 5kHz 75 00Hz N N 31 500 800X600 60Hz 37 9kHz 60 317Hz P P 40 000 800x600 75Hz 46 9kHz 75 00Hz P P 49 500 800X600 85Hz 53 7kHz 85 06Hz P P 56 250 1024x768 60Hz 48 4kHz 60 01Hz N N 65 000 1024X768 75Hz 60 0kHz 75 03Hz P P 78 750 720x400 70Hz 31 46kHz 70 08Hz N P 28 320 1366X768 60 47 7KHZ 60 00HZ P N...

Page 22: ...LCD analog display monitors use a 15 Pin Mini D Sub connector as video input source Pin Description 1 Red 2 Green 3 Blue 4 Ground 5 Ground 6 R Ground 7 G Ground 8 B Ground 9 5V for DDC 10 Ground 11 No Connection 12 SDA 13 H Sync Composite Sync 14 V Sync 15 SCL Table 1 1 15 5 10 6 11 ...

Page 23: ...gative c Video Amplitude RGB 0 7Vp p d Frequency H support to 30K 70KHz V support to 50 85Hz Pixel Clock support to 110MHz HDMI CONNECT PIN ASSIGNMENT PIN SIGNAL ASSIGNMENT PIN SIGNAL ASSIGNMENT 1 TMDS Data2 11 TMDS Clock Shield 2 TMDS Data2 Shield 12 TMDS Clock 3 TMDS Data2 13 CEC 4 TMDS Data1 14 Reserved N C on device 5 TMDS Data1 Shield 15 SCL 6 TMDS Data1 16 SDA 7 TMDS Data0 17 DDC CEC Ground ...

Page 24: ...nal Digital HD a Pin Assignment Refer to Table 2 b Type A c Polarity Positive or Negative d Frequency H 15 734KHz V 60Hz NTSC 480i H 31KHz V 60Hz NTSC 480p H 45KHz V 60Hz NTSC 720p H 33KHz V 60Hz NTSC 1080i Four Pin mini DIN S Video Connector a Pin Assignment ...

Page 25: ...CONFIDENTIAL DO NOT COPY Page 5 4 File No SG 0176 b Signal Level Video Y Analog 0 1Vp p 75Ω Video C Analog 0 286p p 75 Sync H V 0 3V below Video Y Frequency H 15 734KHz V 60Hz NTSC ...

Page 26: ...c Frequency 55 801MHz NTSC ATSC System a IF output level 1Vp p minimum b System ATSC c Frequency 57 863MHz ATSC Component signal Analog HD1 and Analog HD2 Analog HD1 a Frequency H 15 734KHz V 60Hz NTSC 480i H 31KHz V 60Hz NTSC 480p H 45KHz V 60Hz NTSC 720p H 33KHz V 60Hz NTSC 1080i b Signal level Y 1Vp p Pb 0 350Vp p Pr 0 350Vp p c Impedance 75Ω ...

Page 27: ... H 31KHz V 60Hz NTSC 480p H 45KHz V 60Hz NTSC 720p H 33KHz V 60Hz NTSC 1080i b Signal level Y 1Vp p Pb 0 350Vp p Pr 0 350Vp p c Impedance 75Ω RCA type Yellow Composite Video Connector AV1 AV2 AV3 a Signal Level Video Y C Analog 1Vp p 75 Sync H V 0 3V below Video Y C b Frequency H 15 734KHz V 60Hz NTSC ...

Page 28: ...CONFIDENTIAL DO NOT COPY Page 5 7 File No SG 0176 PHONE JACK AUDIO INPUT a Signal Level 1Vrms b Frequency Response 250Hz 20KHz ...

Page 29: ...V 240V AC 10 50 60 HZ into DC 5V 12V 24Vsource The main board receives different types of video signal into the MTK8205 Ic Afterward the MTK8205 Ic process the signals control the various functions of the monitor and outputs control signal video signal and power to the 37 WXGA panel to be displayed The power send to the panel is first processed by the inverter ...

Page 30: ...ay device The analog audio of s video YPbPr TV PC and A V is transmitting to the WM8776 processed The purpose is process the input audio signal to control volume bass treble surround and balance The HDMI video and audio is must transmitting to sil9011 processed then TMDS signal to the MTK8205 generates the vertical and horizontal timing signals for display device The DTV signal is processes to the...

Page 31: ...Size Document Number Rev Date Sheet of IDTQS3VH257 L For DTV Signal MM1492 L Video Signal U21 L 37 LCD Panel Sil9011 U16 Communicate Signal SIF L Audio Signal R 12V PHILIPS FQ1236 TU1 Y HDMI CON P1 Control Pin R KEY BOARD CONN A V RCA P2 24C02 U17 FFC 50PIN CON 5V IR CONN DVI Audio Input P7 POWER CONN AV3 RCA J4 TDA8946 UA1 HEAD PHONE DETECT V U20 U9 Y C CVBS2 L R PC Audio Input P5 L S VIDEO J6 CV...

Page 32: ...QS3VH257 Doc RevCode Title B 1 1 Monday November 14 2005 Title Size Document Number Rev Date Sheet of DTV Backend Decoder MT5351 U10 For Main Board Demodulator MT5111 U9 FCC 50PIN CON J1 VOLTAGE CONTROL CRYSTAL OSCILLATOR X1 AGC Amplifiers U8 I2C PHILIPS TD1336 U6 IF AGC Flash Memory U15 PORT SAW FILTER U7 DDR SDRAM U12 U13 AUD_CTRL Communicate Signal ...

Page 33: ...d I o Connections J7 CONNECTION TOP BOTTOM Pin Description 1 Auto 2 Left 3 Right 4 Down 5 Gnd 6 Up 7 Menu 8 Source 9 Power 10 LED 11 IR 12 5V J1 CONNECTION TOP BOTTOM Pin Description 1 POWRSW 2 12V 3 12V 4 12V 5 GND 6 GND 7 GND 8 GND 9 5V 10 5V 11 5V 12 PWM 13 BL ON OFF ...

Page 34: ...ion Pin Description 1 3 3V 16 HPR 2 GND 17 HPL 3 G Y 18 GNDV 4 B U 19 HPDET 5 R V 20 AV3_IN 6 LMAIN1 21 AV3_GND 7 RMAIN1 22 AV3L 8 5 0V 23 AV3L GND 9 GND 24 AV3R 10 8302IR 25 AV3R GND 11 8302NET1 26 S1Y_IN 12 8302NET2 27 S1Y_GND 13 8302RXD 28 S1C_IN 14 8302TXD 29 S1C_GND 15 GNDV 30 SVDET2 ...

Page 35: ...OREADY 29 VOG1 5 ORESET 30 VOG0 6 GND 31 GND 7 VOPCLK 32 VOB7 8 VODE 33 VOB6 9 VOVSYNC 34 VOB5 10 VOHSYNC 35 VOB4 11 GND 36 GND 12 VOR7 37 VOB3 13 VOR6 38 VOB2 14 VOR5 39 VOB1 15 VOR4 40 VOB0 16 GND 41 GND 17 VOR3 42 AO1SDATA0 18 VOR2 43 AO1LRCK 19 VOR1 44 AO1BCK 20 VOR0 45 AO1MCLK 21 GND 46 GND 22 VOG7 47 U2RX 23 VOG6 48 U2TX 24 VOG5 49 U0RX 25 VOG4 50 U0TX ...

Page 36: ...CONFIDENTIAL DO NOT COPY Page 7 4 File No SG 0176 J8 CONNECTION TOP BOTTOM Pin Description 1 5V 2 GND 3 GND 4 12V 5 12V ...

Page 37: ... and S Video signal is transmission signal to main board MM1492 Switch and output to MTK8205 the MTK8205 generates the vertical and horizontal timing signals for display device The operation of TV route TV signal is processes to the tuner and output to MM1492 switch then transfer to MTK8205 the MTK8205 generates the vertical and horizontal timing signals for display device Audio is processes to th...

Page 38: ... to HDTV It includes 3D comb filter TV Decoder to retrieve the best image from popular composite signals On chip advanced motion adaptive de interlacer converts accordingly the interlace video into progressive one with overlay of a 2D Graphic processor Optional 2nd HDTV or SDTV inputs allows user to see multi programs on same screen Flexible scalar provides wide adoption to various LCD panel for d...

Page 39: ...CONFIDENTIAL DO NOT COPY Page 8 3 File No SG 0176 BOLOCK DIAGRAM 1 Video input a Input Multiplexing 1 component X2 2 composite X3 3 s videoX1 4 HDMI X1 5 VGA X1 6 RF X2 ...

Page 40: ...system Frequency 55 801MHZ 7 support ATSC system Frequency 57 863MHZ 2 TV Decoder For pip pop Dual identical TVD on chip 3D comb for both path Dual VBI decoders for the application of V chip 3 Support Formats Support NTSC NTSC 4 43 Support ATSC Automatic Luma Chroma gain control Automatic TV standard detection NTSC Motion Adaptive 3D comb filter Motion adaptive 3D Noise Reduction VBI decoder for c...

Page 41: ...anes Support alpha blending among these two planes and video Support text bitmap decoder Support line rectangle gradient fill Support bitblt Support color key function Support clip mask 65535 256 16 4 2 color bitmap format OSD Automatic vertical scrolling of OSD image Support OSD mirror and upside down ...

Page 42: ...Input Output AE26 VGASDA Input Output AB23 REQUEST Input Output AB24 READY Input Output AD22 SCL Input Output AC22 SDA Input Output OBO0 SOURCE Input Key detection OBO1 MENU Input Key detection OBO2 UP Input Key detection OBO3 DOWN Input Key detection OBO4 RIGHT Input Key detection OBO5 LEFT Input Key detection OBO6 AUTO Input Key detection OBO7 POWER Input Key detection OGO5 LED Output AF24 IR In...

Page 43: ...gital HD1 HDMI H X 9 9 9 9 X X X X RGB I X 9 9 9 9 X X X X Input Matrix for Windowing Functionality 6 Video processor a Color management Flesh tone and multiple color enhancement Gamma anti Gamma correction Color Transient Improvement CTI Saturation hue adjustment Contrast Brightness Sharpness Management Sharpness and DLTI DCTI Brightness and contrast adjustment Black level extender White peak lev...

Page 44: ...ma scaling Programmable Zoom viewer Picture in picture PIP Picture in picture d Display 12 10 10 8 8 6 Dithering processing for LCD display 10bit gamma correction Support Alpha blending for Video and two OSD panel Frame rate conversion 7 DRAM Usage 8205 2pcs of 8X16 DDR166 is necessary Here is a comparison chart between 2XDDR and 1XDDR MTK8205 8MX16 DDRAM test report ...

Page 45: ...OT COPY Page 8 9 File No SG 0176 8 Flash Usage Flash is used to store FW code fonts bitmaps and big tables for VGA Video and Gamma 2Mbyte is recommended to build a general TV model MTK8205 Flash ROM support test report ...

Page 46: ...CONFIDENTIAL DO NOT COPY Page 8 10 File No SG 0176 DDR SDRAM M13S128168A 6T Application Pin description ...

Page 47: ...y be undefined Apply VDD before or at the same time as VDDQ Apply VDDQ before or at the same time as VTT VREF 2 Start clock and maintain stable condition for a minimum of 200us 3 The minimum of 200us after stable power and clock CLK CLK apply NOP take CKE high 4 Issue precharge commands for all banks of the device 5 Issue EMRS to enable DLL To issue DLL Enable command provide Low to A0 High to BA0...

Page 48: ...st be written after EMRS setting for proper DDR SDRAM operation The mode register is written by asserting low on CS RAS CAS WE and BA0 The DDR SDRAM should be in all bank recharge with CKE already high prior to writing into the mode register The state of address pins A0 A11 in the same cycle as CS RAS CAS WE and BA0 going low is written in the mode register Two clock cycles are requested to comple...

Page 49: ...arge each bank respectively or all banks simultaneously The bank select addresses BA0 BA1 are used to define which bank is precharged when the command is initiated For write cycle tWR min must be satisfied until the precharge command can be issued After tRP from the precharge an active command to the same bank can be initiated Burst Selection for Precharge by Bank address bits A10 AP BA1 BA0 Prech...

Page 50: ...tivation command Bank A to Bank B and vice versa is the Bank to Bank delay time tRRD min 5 Read Bank This command is used after the row activates command to initiate the burst read of data The read command is initiated by activating CS CAS and deasserting WE at the same clock sampling rising edge as described in the command truth table The length of the burst and the CAS latency time will be deter...

Page 51: ... and rising edge of Data Strobe DQS adopted by DDR SDRAM until the burst length is completed 8 Burst Write Operation The Burst Write command is issued by having CS CAS and WE low while holding RAS high at the rising edge of the clock CLK The address inputs determine the starting column address There is no write latency relative to DQS required for burst write cycle The first data of a burst write ...

Page 52: ...ry organized as 1M bytes of 8 bits or 512K words of 16 bits MXIC s Flash memories offer the most cost effective and reliable read write non volatile random access memory The MX29LV800T B MX29LV800AT AB is packaged in 44 pin SOP 48 pin TSOP and 48 ball CSP It is designed to be reprogrammed and erased in system or in standard EPROM programmers ...

Page 53: ...s and data sequences into the command register Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode Table 5 defines the valid register command sequences Note that the Erase Suspend B0H and Erase Resume 30H commands are valid only while the Sector Erase operation is in progress ...

Page 54: ...ce using both standard and Unlock Bypass command sequences An erase operation can erase one sector multiple sectors or the entire device Table indicates the address space that each sector occupies A sector address consists of the address bits required to uniquely select a sector The Writing specific address and data commands or sequences into the command register initiates device operations Figure...

Page 55: ...stics table represents the active current specification for the write mode The AC Characteristics section contains timing specification table and timing diagrams for write operations Figure 1 3 READ RESET COMMAND The read or reset operation is initiated by writing the read reset command sequence into the command register Microprocessor read cycles retrieve array data The device remains enabled for...

Page 56: ...section next 5 RESET COMMAND Writing the reset command to the device resets the device to reading array data Addresses bits are don t care for this command The reset command may be written between the sequence cycles in an erase command sequence before erasing begins This resets the device to reading array data Once erasure begins however the device ignores reset commands until the operation is co...

Page 57: ...ace MT5111 accepts either the direct IF signals centered at 44MHZ or 43 75MHZ or the low IF signal Centered at 5 38MHZ The center frequency of the incoming IF signal can also be programmed to other frequencies for Various applications An On chip programmable gain controlled amplifier is designed to provide sufficient signal amplitude when the received RF signal is weak The If signal is first sampl...

Page 58: ...transport stream packets The chip finally outputs the decoded MPEG 2 packets in either the serial or parallel transport stream format In addition to the demodulation of HDTV signal MT5111 also provides the capability to remove the NTSC co channel interference To achieve the best reception condition an antenna interface compliant with EIA CEA 909 is designed to control the antenna parameters MT5111...

Page 59: ...upport flexible transport demux HD MPEG 2 video decoder JPEG decoder MPEG1 2 MP3 AC3 audio decoder HDTV encoder The MT5351 enables consumer electronics manufactures to build high quality feature rich DTV STB or other home entertainment audio video device World Leading Technology HW support worldwide major broadcast network and CA standards include ATSC DVB OpenCable DirectTV MHP Rich Feature for h...

Page 60: ...upport TS recording via IEEE1394 interface C MPEG2 Decoder 1 Support dual MPEG 2 HD decoder or up to 8 SD decoder 2 Complaint to MP ML MP HL and MPEG 1 video standards D JPEG Decoder 1 Decode Base line or progressive JPEG file E 2D Graphics 1 Support multiple color modes 2 Point horizontal vertical line primitive drawing 3 Rectangle fill and gradient fill functions 4 Bitblt with transparent alpha ...

Page 61: ...Picture PIP 5 Picture Out Picture POP 6 480i 576i 480p 576p 720p 1080i output I Auxiliary Display 1 Mixing one video and one OSD 2 480i 576i output J TV Encoder 1 Support NTSC M N PAL M N B D G H I 2 Macrovision Rev 7 1 L1 3 CGMS WSS 4 Closed Captioning 5 Six 12 bit video DACs for CVBS S video or RGB YPbPr output K Digital Video Interface 1 Support SAV EAV 2 Support 8 16 for SD HD digital video in...

Page 62: ...rround processing include virtual surround 10 Audio and video lip synchronization 11 Support reverberation 12 SPDIF out 13 I2S I F O Peripherals 1 Three UARTs with Tx and Rx FIFO two of them have hardware flow control 2 Two serial interfaces one is master only the other can be set to master mode or slave mode 3 Two PWMs 4 IR blaster and receiver 5 IEEE1394 link controller 6 IDE bus ATA ATAPI7 UDMA...

Page 63: ...and output enable OE controls MXIC s Flash memories augment EPROM functionality with in circuit electrical erasure and programming The MX29LV320AT B uses a command register to manage this functionality MXIC Flash technology reliably stores memory contents even after 100 000 erase and program cycles The MXIC cell is designed to optimize the erase and program mechanisms In addition the combination o...

Page 64: ...CONFIDENTIAL DO NOT COPY Page 8 28 File No SG 0176 ...

Page 65: ...CONFIDENTIAL DO NOT COPY Page 8 29 File No SG 0176 BLOCK DIAGRAM ...

Page 66: ...tions may also be implemented via programming equipment See the Sector Group Protection and Chip Unprotection section 3 If WP ACC VIL the two outermost boot sectors remain protected If WP ACC VIH the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in Sector Sector Block Protection and Unprotection If WP ACC VHH all sectors ...

Page 67: ...ter command sequences Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data Section has details on erasing a sector or the entire chip or suspending resuming the erase operation After the system writes the Automatic Select command sequence the device enters the Automatic Select mode The system can then read Automatic Select codes...

Page 68: ...Reset command is required to return to the read mode when the device is in the Automatic Select mode or if Q5 goes high 4 The fourth cycle of the Automatic Select command sequence is a read cycle 5 The data is 99h for factory locked and 19h for not factory locked 6 The data is 00h for an unprotected sector sector block and 01h for a protected sector sector block In the third cycle of the command s...

Page 69: ...d low power consumption such as handy terminals To active this mode MX29LV320AT B automatically switch themselves to low power mode when MX29LV320AT B addresses remain stable during access time of tACC 30ns It is not necessary to control CE WE and OE on the mode Under the mode the current consumed is typically 0 2uA CMOS level RESET OPERATION 01The RESET pin provides a hardware method of resetting...

Page 70: ... sectors were last set to be protected or unprotected That is sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in Sector Sector Group Protection and Chip Unprotection Note that the WP ACC pin must not be left floating or unconnected inconsistent behavior of the device may result SOFTWARE COMMAND DEFINITION...

Page 71: ...ded sector will cause Q2 to toggle 2 Performing successive read operations from any address will cause Q6 to toggle 3 Reading the byte word address being programmed while in the erase suspend program mode will indicate logic 1 at the Q2 bit However successive reads from the erase suspended sector will cause Q2 to toggle Fig C COMMAND WRITE OPERATION ...

Page 72: ...CONFIDENTIAL DO NOT COPY Page 8 36 File No SG 0176 Fig D READ TIMING WAVEFORMS ...

Page 73: ...CONFIDENTIAL DO NOT COPY Page 8 37 File No SG 0176 Fig E RESET TIMING WAVEFORM ...

Page 74: ... and two corresponding n bit wide one half clock cycle data transfers at the I O pins Read and write accesses to the DDR SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence Accesses begin with the registration of an Active command which is then followed by a Read or Write command The address bits registered coinc...

Page 75: ... Functional Block Diagram is intended to facilitate user understanding of the operation of the device it does not represent an actual circuit implementation Note DM is a unidirectional signal input only but is internally loaded to match the load of the bidirectional DQ and DQS signals ...

Page 76: ...CONFIDENTIAL DO NOT COPY Page 8 40 File No SG 0176 Pin Configuration 400mil TSOP II x4 x8 x16 ...

Page 77: ...e Register Set command with bits A7 and A9 A12 each set to zero bit A8 set to one and bits A0 A6 set to the desired values A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode All other combinations of values for A7 A12 are reserved for future use and or test modes Test modes and reserved states should not be u...

Page 78: ... are controlled via the bit settings shown in the Extended Mode Register Definition The Extended Mode Register is programmed via the Mode Register Set command with BA0 1 and BA1 0 and retains the stored information until it is programmed again or the device loses power The Extended Mode Register must be loaded when all banks are idle and the controller must wait the specified time before initiatin...

Page 79: ...th Auto Precharge disabled this command is undefined and should not be used for read bursts with Auto Precharge enabled or for write bursts 9 Deselect and NOP are functionally interchangeable Active The Active command is used to open or activate a row in a particular bank for a subsequent access The value on the BA0 BA1 inputs selects the bank and the address provided on inputs A0 A12 selects the ...

Page 80: ...npersistent so it must be issued each time a refresh is required The refresh addressing is generated by the internal refresh controller This makes the address bits Don t Care during an Auto Refresh command The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7 8μs maximum Self Refresh The Self Refresh command can be used to retain data in the DDR SDRAM even if the re...

Page 81: ...M along with output data The initial low state on DQS is known as the read preamble the low state coincident with the last data out element is known as the read postamble Upon completion of a burst assuming no other commands have been initiated the DQs and DQS goes High Z Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command In either case a contin...

Page 82: ...CONFIDENTIAL DO NOT COPY Page 8 46 File No SG 0176 Random Read Accesses CAS Latencies Burst Length 2 4 or 8 ...

Page 83: ...lowing the write command and subsequent data elements are registered on successive edges of DQS The Low state on DQS between the Write command and the first rising edge is known as the write preamble the Low state on DQS following the last data in element is known as the write postamble The time between the Write command and the first corresponding rising edge of DQS tDQSS is specified with a rela...

Page 84: ...d on any positive edge of clock following the previous Write command The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated The new Write command should be issued x cycles after the first Write command where x equals the number of desired data element pairs pairs are require...

Page 85: ...t Etch ADC channel has programmable gain control with automatic level control Digital audio output word lengths from 16 32 bits and sampling rates from 32kHZ to 96KHZ are supported The DAC has an input mixer allowing an external analogue signal to be mixed with the DAC signal There are also Headphone and line outputs with control for the headphone The WM8776 supports fully independent sample rates...

Page 86: ...rate The master clock is used to operate the digital filters and the noise shaping circuits In slave mode the WM8776 has a master detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate to within 32 system clocks If there is a greater than 32 clocks error the interface is disabled and ADCLRC DACLRC for optical performance although t...

Page 87: ...LRC ADCBCLK DACBCLK are input to the WM8776 DIN and DACLRC are sampled by the WM8776 on the rising edge of DACBCLK ADCLRC is sampled on the rising edge of ADCBCLK ADC data is output on DOUT and changes on the falling edge of ADCBCLK By setting control bit BCLKINV the polarity of ADCBCLK and DACBCLK may be reversed so that DIN and DACLRC are sample on the falling edge of DACBCLK ADCLRC is sampled o...

Page 88: ...nd each device has a uni ue 7 bit address this is not the same as the 7 bit address of each register in the wm8776 The wm8776 operates as a slave device only 2 wire serial interface as shown in the following figure The wm8776 has two possible device addresses which can be selected using the CE pin In the L37 LCD TV CE pin is LOW device address is 34h In the L37 wm8776 has 2 wire interface ...

Page 89: ...omplete solution for receiving HDMI compliant digital audio and video Specialized audio and video processing is available within the sil9011 to easily and cost effectively adds HDMI capability to consumer electronics devices such as digital TVs plasma displays LCD TVs and projectors BLOCK DIAGRAM ...

Page 90: ... can monitor the presence of this 5V supply and if and when necessary provide a fast audio mute without pops when it senses the HDMI cable pulled The microcontroller can also poll registers in the sil9011 to check whether an HDMI cable is connected 3 HDCP Decryption engine The HDCP decryption engine contains all necessary logic to decrypt the incoming audio and video data The decryption process is...

Page 91: ...ning up to 400KHZ This bus is used to configure the SIL9011 by reading writing to the appropriate registers The SIL9011 is accessible on the local I2 c bits at two device address The logic state of the CI2CA pin is latched on the rising edge of REST providing a choice of two pairs of device address Control of local I2 c address with CI2CA pin MM1942 Application The MM1942 IC is a 5 input 2 output ...

Page 92: ...ata are transmitted and received in the units of byte and Acknowledge It is transmitted by MSB first from the Start conditions The data format is set as shown in the following figure In the L32 TV MM1492 slave address ADR terminal is L and 90H is selected The following figure indicates the control contents of control registers and switches ...

Page 93: ...CONFIDENTIAL DO NOT COPY Page 8 57 File No SG 0176 2 Switch control table a Video output 1 b Audio output 1 c Audio gain ...

Page 94: ...figuration The TDA8946AJ inputs can be driven symmetrical floating as well as asymmetrical In the asymmetrical mode one input pin is connected via a capacitor to the signal source and the other input is connected to the signal ground The signal ground should be as close as possible to the SVR electrolytic capacitor ground Note that the DC level of the input pins is half of the supply voltage VCC s...

Page 95: ... 8 59 File No SG 0176 2 Output power measurement The output power as a function of the supply voltage is measured on the output pins at THD 10 in the L32 LCD TV Vcc 12V so we can see as shown in the following figure output about 7W ...

Page 96: ...g the proper DC voltage to pin MODE a Mute In this mode the amplifier is DC biased but not operational no audio output This allows the input coupling capacitors to be charged to avoid pop noise The device is in mute mode when 3 5 V VMODE VCC 1 5 V b Operating In this mode the amplifier is operating normally The operating mode is activated at VMODE 1 0V ...

Page 97: ...CONFIDENTIAL DO NOT COPY Page 9 1 File No SG 0176 Chapter 9 Waveforms 1 PC MODE 1366X768 60HZ CH1 H sync FB46 CH2 V sync FB45 GREEN R194 ...

Page 98: ...CONFIDENTIAL DO NOT COPY Page 9 2 File No SG 0176 CH1 VGAHSYNC FB46 CH2 VGAVSYNC FB45 CH1 VGAVSYNC FB45 CH2 GREEN R194 ...

Page 99: ...CONFIDENTIAL DO NOT COPY Page 9 3 File No SG 0176 CH1 VGAL CE81 CH2 AVOL R252 CH1 AUSPL RA12 CH2 L UA1 PIN17 ...

Page 100: ...CONFIDENTIAL DO NOT COPY Page 9 4 File No SG 0176 CH1 XTALI U9 PIN A15 CH2 XTALO U9 PIN B15 2 AV TV MODE AV1 AV2 AV3 TV VIDEO CH1 R88 CH2 Q4 PIN1 ...

Page 101: ...CONFIDENTIAL DO NOT COPY Page 9 5 File No SG 0176 CH1 CVBS1 U9 PINA2 CH2 CVBS1 R136 CH1 AV1L U20 PIN1 CH2 AUO1L_SWO U20 PIN36 ...

Page 102: ...CONFIDENTIAL DO NOT COPY Page 9 6 File No SG 0176 CH1 AUSPL RA12 CH2 L UA1 PIN17 CH1 D_CLK U11 PIN46 CH2 D_DQ15 U11 PIN65 ...

Page 103: ...CONFIDENTIAL DO NOT COPY Page 9 7 File No SG 0176 CH1 DACMCLK U22 PIN11 CH2 DOUT U22 PIN12 CH1 SCL34H U22 PIN19 CH2 SDA34H U22 PIN18 ...

Page 104: ...CONFIDENTIAL DO NOT COPY Page 9 8 File No SG 0176 3 ANALOG HD MODE ANALOG HD1 HD2 CH1Y1_IN R105 CH2 Y U21 PIN7 CH1Y R280 CH2 Y C120 ...

Page 105: ...CONFIDENTIAL DO NOT COPY Page 9 9 File No SG 0176 CH1 TUL U20 PIN44 CH2 AUO1L_SWO U20 PIN 36 CH1 AUSPL RA12 CH2 L UA1 PIN17 ...

Page 106: ...CONFIDENTIAL DO NOT COPY Page 9 10 File No SG 0176 4 DIGITAL HD CH1 DATA2 P1 PIN 1 CH2 DATA2 P1 PIN3 CH1 HDMI0 U16 PIN 124 CH2 HDMI15 U16 PIN 102 ...

Page 107: ...CONFIDENTIAL DO NOT COPY Page 9 11 File No SG 0176 CH1 XTLI U16 PIN85 CH2 XTLO U16 PIN86 CH1 HDMISDA U16 PIN39 CH2 HDMISCL U16 PIN40 ...

Page 108: ...CONFIDENTIAL DO NOT COPY Page 9 12 File No SG 0176 DTV Mode Video Board CH1 AO1BCK J1 Pin 7 CH2 AO1SDATA0 J1 PIN 9 CH1 VOPCLK J1 Pin 44 CH2 VOB0 J1 PIN 11 ...

Page 109: ...CONFIDENTIAL DO NOT COPY Page 9 13 File No SG 0176 CH1 VOPCLK J1 Pin 44 CH2 VOG0 J1 PIN 21 CH1 VOPCLK J1 Pin 44 CH2 VOR0 J1 PIN 31 ...

Page 110: ...CONFIDENTIAL DO NOT COPY Page 9 14 File No SG 0176 CH1 XTAL1 C63 CH2 XTAL2 C62 CH1 OPWM0 R42 CH2 OXTALI R43 ...

Page 111: ...CONFIDENTIAL DO NOT COPY Page 9 15 File No SG 0176 5 POWER ON OFF CH1 DV120B F1 CH2 GPIO R3 POWER ON ...

Page 112: ...CONFIDENTIAL DO NOT COPY Page 9 16 File No SG 0176 CH1 DV120B F1 CH2 GPIO R3 POWER OFF CH1 DV50B U7 PIN8 CH2 GPIO R3 POWER ON ...

Page 113: ...CONFIDENTIAL DO NOT COPY Page 9 17 File No SG 0176 CH1 DV50B U7 PIN8 CH2 GPIO R3 POWER OFF CH1 DV120B U6 PIN1 CH2 AV_V90 U6 PIN3 POWER ON ...

Page 114: ...CONFIDENTIAL DO NOT COPY Page 9 18 File No SG 0176 CH1 DV120B U6 PIN1 CH2 AV_V90 U6 PIN3 POWER OFF CH1 DV50A U4 PIN1 CH2 DV33A F3 AC POWER ON ...

Page 115: ...CONFIDENTIAL DO NOT COPY Page 9 19 File No SG 0176 CH1 DV50A U4 PIN1 CH2 DV33A F3 AC POWER OFF CH1 DV33A U5 PIN 1 CH2 DV18A U5 PIN2 AC POWER ON ...

Page 116: ...CONFIDENTIAL DO NOT COPY Page 9 20 File No SG 0176 CH1 DV33A U5 PIN 1 CH2 DV18A U5 PIN2 AC POWER OFF CH1 DV50B U14 PIN 3 CH2 DV25 U14 PIN2 POWER ON ...

Page 117: ...CONFIDENTIAL DO NOT COPY Page 9 21 File No SG 0176 CH1 DV25 U13 PIN7 CH2 D1V25 U13 PIN3 POWER OFF CH1 GPIO R3 CH2 LVDS SEQ R10 POWER ON ...

Page 118: ...CONFIDENTIAL DO NOT COPY Page 9 22 File No SG 0176 CH1 GPIO R3 CH2 LVDS SEQ R10 POWER OFF CH1 GPIO R3 CH2 ATSC SW R121 POWER ON ...

Page 119: ...CONFIDENTIAL DO NOT COPY Page 9 23 File No SG 0176 CH1 GPIO R3 CH2 ATSC SW R121 POWER OFF ...

Page 120: ...4 3 3V working ok LED is lighting It is in power saving 1 Check video cable 2 Is the timing supported 3 Check sync input 4 Check VGASOG rout if analog SOG Is backlight on 1 Check J1 PIN 1 2 Is inverter ok U9 no data out It means data to LVDS 1 Is J6 connecting well 2 Check J1 5V 12V 3 Is panel ok U9 no data in 1 Is U9 working good 2 Is U11 U12 working good 3 IS U10 working good 1 Check P3 D sub In...

Page 121: ...U20 input correct 1 Check P2 signal 2 Check signal between P2 and U20 IF AV1 AV2 mode 3 Check Tuner U20 IF TV mode 4 Check J4 J6 IF AV3 S Video 5 Check U20 POWER 9V 6 Check U22 data input output LVDS output correct 1 Check signal between U20 and U9 1 Chcak J6 Connect is good 2 Is panel working ok END U20 output correct 1 Check signal between U20 and U9 2 Check U9 clock 27MHz 3 Check U9 power ...

Page 122: ...CTLY Start Input signal good 1 Check video 2 Check host s setting U21 input correct 1 Check signal between P8 U21 2 Check U21 power 3 3V U9 input correct 1 Check signal between U21 U9 2 Check U9 Clock 27MHZ LVDS output correct 1 Check U9 2 Check U9 power 3 3V 1 8V 1 Is J6 connected good 2 Is panel working ok END ...

Page 123: ...SPLAY CORRECTLY Input signal good Start 1 Check video 2 Check host s setting U16 input correct 1 Check p1 connect 2 Check signal between P1 and U16 U16 no data out 1 Check U16 power 2 Check between signal U16 and U9 3 Check clock 28 224MHZ 1 Is J6 connected good 2 Is panel working ok END ...

Page 124: ...Check power cable connection J1 U7 pin 5 6 7 8 The voltage is about 5V while power switch on 1 J1 connection good 2 Check U9 GPIO Pin U4 pin2 The voltage is about 3 3V 1 J1 to connection good 2 Check U4 U6 pin 3 The voltage is about 9V 1 Check U9 GPIO Pin 2 Check U6 U5 pin2 The voltage is about 1 8V 1 Check J1 Connect 2 Check U5 L5 U14 pin2 The voltage is about 2 5V while power switch on 1 Check U...

Page 125: ...0 TROUBLE OF DDC READING Start Analog DDC OK Support DDC1 2B 1 Analog cable ok 2 Check signal U18 to P3 3 Check U18 Voltage 4 Is compliant protocol HDMIDDC OK Support DDC1 2B 1 Analog cable ok 2 Check signal U17 to P1 3 Check U17 Voltage 4 Is compliant protocol END ...

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