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A.
Scaling controller
General
Embedded dual DDC support DDC1
and
DDC2B,CI
Zoom scaling up and down
Embedded Pattern Generator
No external memory required.
Require only one crystal
to generate all timing
Embedded reset control output
Embedded crystal output to MICROP
3 channels 8 bits PWM output, and selectable PWM clock frequency.
PIN DESCRIPTION
(I/O Legend: A= Analog, I=Input, O=Output, P=Power, G=Ground)
■
ADC: 15 pins
Name I/O
Pin
No
Description
Note
ADC_ GND
AG
27
ADC ground
ADC_REFIO
AP
28
ADC band-gap voltage de-coupling
1.20V
ADC_VDD AP
29
Analog
power
(3.3V)
BLUE+
AI
30
Analog input from BLUE channel
BLUE-
AI
31
Analog input ground from BLUE channel
ADC_ GND
AG
32
ADC ground
SOG/ADC_TEST
AIO
33
SOG in/ADC test pin
GREEN+
AI
34
Analog input from GREEN channel
GREEN-
AI
35
Analog input ground from GREEN channel
ADCB_VDD AP
36
Analog
power
(3.3V)
RED+
AI
37
Analog input from RED channel
RED_
AI
38
Analog input ground from RED channel
ADC_GND AG
39
Analog
ground
ADC_GND AG
40
Analog
ground
ADC_VDD AP
41
Analog
power
(3.3V)
AHS
AI
42
Analog HS input
(10), (4), (5)
AVS
AI
43
Analog VS input
(2), (4), (5)
■
PLL:8 pins
Name I/O
Pin
No
Description
Note
XO AI
1
Reference
clock
output
XI
AO
2
Reference clock input
DPLL GND
AG
3
Ground for digital PLL
DPLL VDD
AP
4
Power for digital PLL
(3.3V)
APLL VDD
AP
5
Power for multi-phase PLL
(3.3V)
PLL TEST1
AIO
6
Test Pin 1 / IRQ#
3.3V tolerance
PLL TEST2
AIO
7
Test Pin 2/Power-on-latch for crystal out
Frequency
APLL GND
AG
8
Ground for multi-phase PLL
4. Circuit Description
10
ViewSonic
Corporation
Co
nfidential
-
Do
Not
Copy
VE710s/b-2
VA721
Summary of Contents for VS10047
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