UG:123
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Enable/Disable (J10-8 to J10-11, and J10-21 through 24)
The Enable/Disable control pins allow ConverterPAC
™
outputs to be sequenced either on or off. For the
DC MegaPAC
™
, J10-8 through 11 and J10-21 through 24 are the control pins for output positions 1
through 8. For DualPACs
™
, both outputs are sequenced. In parallel arrays, only the driver ConverterPAC
need be controlled. The Enable/Disable pins should be pulled low to less than 0.7V with respect to
Signal Ground to disable the outputs. They will sink 10mA maximum. These pins should be open
circuited or allowed to exceed 4.5V when enabled. Do not apply more than 6V to these inputs at any
time. If driven from an electromechanical switch or relay, a capacitor should be connected to eliminate
the effects of switch bounce.
General Shutdown /GSD (J10-5)
The GSD control pin on J10-5 allows simultaneous shutdown of all ConverterPAC outputs (see Figure 4).
This pin must be pulled down to less than 0.7V, and will sink 10mA maximum to shut down all outputs.
The GSD pin should be open circuited or allowed to exceed 4.5V when not in use, or when the outputs
are to be enabled. Do not apply more than 6V to this input at any time. Normal open circuit voltage is
1.5 – 3V with respect to Signal Ground. If driven from an electromechanical switch or relay, a capacitor
should be connected to eliminate the effects of switch bounce.
J10 INTERFACE CONNECTOR IDENTIFICATION
1 Signal Ground
14 No Connection
2 Signal Ground
15 Signal Ground
3 Overtemp. Warning
16 VCC +5 volt, 300mA
4 Analog Temperature
17 VCC +5 volt, 300mA
5 General Shutdown
18 Input Power OK
6 No Connection
19 Input Power Fail
7 No Connection
20 No Connection
8 Enable/Disable #8
21 Enable/Disable #7
9 Enable/Disable #6
22 Enable/Disable #5
10 Enable/Disable #4
23 Enable/Disable #3
11 Enable/Disable #2
24 Enable/Disable #1
12 Signal Ground
25 Gate Out Slot #8
13 Gate In Slot #1
Amp 25-pin connector #746862-2
plug for flat ribbon cable. Mates with
housing Amp #747548-2 plus slide
latch or similar.
2 3 4 5 6 7
1
8 9 10 11 12 13
14 15 16 17 18 19 20 21 22 23 24 25
J10
Figure 4
Interface Connector
DC MegaPAC
24
1
5
Signal Ground
General Shutdown
Enable/Disable Output 1
J10
1
0
TTL "1" (OFF)
TTL "0" (ON)
A TTL "1" applied to the base of the transistor turns
output OFF. Pin 1 (or Pin 12 for GSD) is pulled Low
with respect to Signal Ground.
16
VCC
Enable/Disable Control
Figure 5
Enable/Disable and
General Shutdown
