Chapter 3
Diphase Testing
Conditioned Diphase encoding
Data Communications and Diphase Testing Manual
January 2016
21148872, Rev. 002
Page 25
Conditioned Diphase encoding
In Conditioned Diphase encoding, the phase transition for each bit is determined by the
phase transition for the previous
encoded bit
.
•
Each time the data signal is a logic level 0, the phase transition is the same as
that for the previous encoded bit.
–
If the previous bit used a high to low phase transition (
), the 0 is also encoded using
a high to low phase transition.
–
If the previous bit used a low to high phase transition (
), the 0 is also encoded using
a low to high phase transition.
•
Each time the data signal is logic level 1, the phase transition is inverted.
–
If the previous bit used a high to low phase transition (
), the 1 is encoded using a low
to high phase transition (
).
–
If the previous bit used a low to high phase transition (
), the 1 is encoded using a
high to low phase transition (
).
for an illustration of a Conditioned Diphase encoded bit pattern of
101001100.
The signal level changes occur at the one half bit interval point.
Specifying the clock frequency
The first step in Diphase testing is to specify the clock frequency for the instrument in
Kilohertz.
To specify the clock frequency
1
Select the
Setup
soft key, then select the
Timing
setup tab.
2
Specify the frequency in Kilohertz.
The frequency is specified.
Figure 6
Conditioned Diphase encoding
