VIA Technologies EPIA, User Manual

Page: 58 / 92

Chapter 3
50
DRAM C
LOCK
/D
RIVE
C
ONTROL
DRAM Clock
Set the DRAM Clock.
Settings: [Host CLK, HCLK-33M, By Auto]
DRAM Timing By SPD
Set the DRAM Timing by SPD.
Settings: [Disabled, Enabled]
SDRAM Cycle Length
Set the DRAM Cycle Length.
Settings: [3, 2]
Bank Interleave
Set the Bank Interleave mode.
Settings: [Disabled, 2 Bank, 4 Bank]