BIOS Setup
47
CPU & PCI B
US
C
ONTROL
: Move
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General Help
Menu Level
Item Help
[By Auto]
VLink mode selection
CPU & PCI Bus Control
Phoenix - AwardBIOS CMOS Setup Utility
VLink 8X Support
[Enabled]
DRDY_Timing
[Default]
V-Link mode selection
This menu item controls the data transfer speed between the north and south
bridge.
Settings: [By Auto, Mode 0~4]
V-Link 8X Support
Settings: [Enabled, Disabled]
DRDY_Timing
Settings: [Slowest, Default, Optimize]
Summary of Contents for EPIA-PN
Page 1: ...User s Manual EPIA PN Version 1 0 June 21 2006...
Page 8: ...iv This page is left intentionally blank...
Page 12: ...Chapter 1 4 MAINBOARD LAYOUT...
Page 13: ...Specifications 5 BACK PANEL LAYOUT...
Page 35: ...27 CHAPTER 3 BIOS Setup This chapter gives a detailed explanation of the BIOS setup functions...