VIA Technologies EPIA-MII, User Manual

Page: 62 / 73

Chapter 3
54
F
REQUENCY
/ V
OLTAGE
C
ONTROL
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency. Settings:
100 MHz, 133 MHz
and
By SPD
DRAM Timing
The value in this field depends on the memory modules installed in your
system. Changing the value from the factory setting is not recommended
unless you install new memory that has a different performance rating than
the original modules. Settings: Manual and By SPD
DRAM CAS Latency
This item adjusts the speed it takes for the memory module to complete a
command. Generally, a lower setting will improve the performance of your
system. However, if your system becomes less stable, you should change it
to a higher setting. This field is only available when “DRAM Timing” is set to
“Manual”. Settings: 2, 2.5