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Chapter 3
50
CPU
&
PCI
B
US
C
ONTROL
: Move
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General
Help
Menu Level
Item Help
[By Auto]
VLink mode selection
CPU & PCI Bus Control
Phoenix - AwardBIOS CMOS Setup Utility
VLink 8X Support
[Enabled]
DRDY_Timing
[Default]
V-Link mode selection
This menu item controls the data transfer speed between the north and south
bridge.
Settings: [By Auto, Mode 0~4]
V-Link 8X Support
Settings: [Enabled, Disabled]
DRDY_Timing
Settings: [Slowest, Default, Optimize]
Summary of Contents for EPIA-EN
Page 1: ...User s Manual EPIA EN Version 1 23 January 18 2012...
Page 4: ......
Page 8: ...iv This page is intentionally left blank...
Page 13: ...Specifications 5 MAINBOARD LAYOUT...
Page 36: ......
Page 37: ...29 CHAPTER 3 BIOS Setup This chapter gives a detailed explanation of the BIOS setup functions...
Page 54: ...Chapter 3 46...
Page 76: ...Chapter 3 68 Settings Disabled 0 20 0 25 0 35...