VESTEL MB130 IDTV, Service Manual

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7. 2GB DDR3 SDRAM
A. HYNIX H5TQ2G63GFR-TEC (U113-U110)
Description
The H5TQ2G63GFR is a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM,
ideally suited for the main memory applications which requires large memory density and high bandwidth.
Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of
the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the
CK), Data, Data strobes and Write data masks inputs are sam-pled on both rising and falling edges of it. The
data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Features

VDD=VDDQ=1.5V +/- 0.075V

Fully differential clock inputs (CK, CK) operation

Differential Data Strobe (DQS, DQS)

On chip DLL align DQ, DQS and DQS transition with CK transition

DM masks write data-in at the both rising and falling edges of the data strobe

All addresses and control inputs except data, data strobes and data masks latched on the rising edges of
the clock

Programmable CAS latency 6, 7, 8, 9, 10, 11, 12 and 13 supported

Programmable additive latency 0, CL-1, and CL-2 supported

Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10

Programmable burst length 4/8 with both nibble sequential and interleave mode

BL switch on the fly

8banks

Average Refresh Cycle (Tcase 0
o
C ~ 95
o
C)
o
7.8 μ s at 0
o
C ~ 85
o
C
o
3.9 μ s at 85
o
C ~ 95
o
C

Auto Self Refresh supported Driver strength selected by EMRS

JEDEC standard 96ball FBGA(x16) Asynchronous RESET pin supported

Driver strength selected by EMRS TDQS (Termination Data Strobe) supported (x8 only)

Dynamic On Die Termination supported 8 bit pre-fetch

Asynchronous RESET pin supported

ZQ calibration supported

Write Levelization supported

On Die Thermal Sensor supported

8 bit pre-fetch