Vertex Standard VXA-300 Pilot III, Service Manual

Page: 8 / 32

8
Transmit Signal Path
Speech input from the microphone is passed through the
microphone amplifier
Q1011-1 ( NJM12902V ), then ap-
plied to the ALC amplifier Q1017 ( AN6123MS ). The am-
plified speech signal is passed through the high-pass fil-
ter
Q1011-3 ( NJM12902V ) and low-pass filter Q1011-4
( NJM12902V ), which adjust the modulation level, then
fed to the AM modulator Q1069 ( 2SC5555ZD ).
When using the optional headset, the SIDETONE signal
from J1002 becomes “HIGH”, turning Pin10 of
Q1024
( LC87F74C8A ) on; pin 91 of Q1024 ( LC87F74C8A ) there-
fore a portion of the speech signal applied to the AF pow-
er amplifier
Q1005 ( TDA2733D ) as a monitor signal.
The carrier signal from the VCO Q1046 ( 2SC5555ZD )
passes through the buffer amplifier Q1049 ( 2SC5555ZD )
and TX/RX switch D1026 ( DAN222 ).
The signal from D1026 ( DAN222 ) is amplified by Q1060
( 2SC5555ZD ) and Q1064 ( RD01MUS1 ), and ultimately
applied to the final amplifier Q1069 ( RD07MVS1 ) which
increases the signal level up to 5 watts output power. The
transmit signal then passes through the antenna switch
D1039 ( RLS135 ), and is low-pass filtered to suppress away
harmonic spurious radiation before delivery to the anten-
na.
Automatic Transmit Power Control
RF power output from the final amplifier is sampled by
C1275/C1279 and is rectified by
D1043 ( HSM88WA ). The
resulting DC is fed through the Automatic Power Con-
troller
Q1074 ( NJM2125F ), thus allowing control of the
power output.
Transmit Inhibit
When the transmit PLL is unlocked, pin 7 of PLL chip
Q1041 ( MB15A01PFV1 ) goes to a logic low. The result-
ing DC “unlock” control voltage is switches off TX inhibit
switches
Q1053 ( DTC144EE ), and Q1055 ( DTA143EE ) to
disable the supply voltage to transmitter RF amplifiers
Q1060 ( 2SC5555ZD ), disabling the transmitter.
Spurious Suppression
Generation of spurious products by the transmitter is min-
imized by the fundamental carrier frequency being equal
to the final transmitting frequency. Additional harmonic
suppression is provided by a low-pass filter consisting of
L1025, L1027 & L1029 and C1271, C1280, C1282, C1285,
C1289 & C1293, resulting in more than 60 dB of harmonic
suppression prior to delivery of the RF signal to the an-
tenna.
Circuit Description
PLL Frequency Synthesizer
PLL circuitry consists of VCO Q1046 ( 2SC5555ZD ), VCO
buffer Q1049 & Q1051 (both 2SC5555ZD ), and PLL sub-
system IC Q1041 ( MB15A01PFV1 ), which contains a ref-
erence divider, serial-to-parallel data latch, programma-
ble divider, phase comparator and charge pump.
Stability is maintained by a regulated 3.5 V supply via
Q1048 ( S-812C35AUA ) which feeds the PLL reference
oscillator Q1041 ( MB15A01PFV1 ), as well as capacitors
associated with the 17.475 MHz frequency reference crys-
tal X1002.
In the receive mode, VCO Q1046 ( 2SC5555ZD ) oscillates
between 143.4 and 172.4 MHz. The VCO output is buff-
ered by
Q1049 & Q1051 (both 2SC5555ZD ), and applied
to the prescaler section of Q1041 ( MB15A01PFV1 ). There
the VCO signal is divided by 64 or 65, according to a con-
trol signal from the data latch section of
Q1041
( MB15A01PFV1 ), before being applied to the program-
mable divider section of Q1041 ( MB15A01PFV1 ). The data
latch section of Q1041 ( MB15A01PFV1 ) also receives se-
rial dividing data from the microprocessor Q1024
( LC87F74C8A ), which causes the pre-divided VCO sig-
nal to be further divided in the programmable divider
section, depending upon the desired receive frequency,
so as to produce a 5 kHz derivative of the current VCO
frequency.
Meanwhile, the reference divider section of Q1041
( MB15A01PFV1 ) divides the 17.475 MHz crystal reference
from the reference oscillator section by 3495 to produce
the 5 kHz loop reference. The 5 kHz signal from the pro-
grammable divider (derived from the VCO) and that de-
rived from the reference oscillator are applied to the phase
detector section of
Q1041 ( MB15A01PFV1 ), which pro-
duces a pulsed output with pulse duration depending on
the phase difference between the input signals. This pulse
train is filtered to DC and returned to the varactor
D1014
( HVC350B ).
Changes in the level of the DC voltage applied to the var-
actors affect the reactance in the tank circuit of the VCO,
changing the oscillating frequency of the VCO according
to the phase difference between the signals derived from
the VCO and the crystal reference oscillator. The VCO is
thus phase-locked to the crystal reference oscillator.
The output of the VCO Q1046 ( 2SC5555ZD ) is buffered
by Q1049 ( 2SC5555ZD ) before application to the 1st mix-
er, as described previously.