VX-261 VHF FM Transceiver Service Manual
7
2. Transmitter System
2-1. MIC Amplifier
The speech signal from internal microphone
MC1001
or external microphone
J1003
is amplified by
Q1044-2
(
NJM12902V
).
The amplified speech signal from
Q1044-2
(
NJM12902V
)
is supplied to pin 14 of Electric Volume IC
Q1018
(
AK2330
) which adjusts the microphone gain through
the TX/RX switch
Q1057-2
(
SN74LV4066A
), high-pass
filter
Q1045-2
(
NJM12902V
), and other TX/RX switch
Q1057-3
(
SN74LV4066A
).
The adjusted speech signal is output from pin 15 of
Q1018
(
AK2330
), and then passed through the limiter ampli-
fier
Q1044-1
(
NJM12902V
), low-pass filter
Q1044-2/-3
(
NJM12902V
), and AF adder
Q1052-3
(
NJM12902V
).
T h e p r o c e s s e d s p e e c h s i g n a l f r o m
Q 1 0 5 2 - 3
(
NJM12902V
) is supplied to pin 22 of Electric Volume
IC
Q1018
(
AK2330
) which adjusts the maximum devia-
tion. The adjusted speech signal is amplified by
Q1052-
2
(
NJM12904R
), and then is made FM modulation to
transmit carrier by the modulator
D1019
(
BB208
) of
VCO
Q1037
(
2SC4227
).
2-2. Drive and Final Amplifier Stages
The modulated signal from the VCO
Q1037
(
2SC4227
)
is buffered by
Q1026
(
2SC5010
). Then the signal is
buffered by
Q1021
(
2SC5010
) and
Q1019
(
2SK3077
)
for the driver amplifier
Q1016
(
RQA0004PXDQS
). The
low-level transmit signal is then applied to
Q1012
(
RQA-
0011DNS
) for final amplification up to 5 watts output
power.
The transmit signal then passes through the antenna
switch
D1003
(
RN142S
) and is low-pass filtered to sup-
press away harmonic spurious radiation before delivery to
the antenna.
2-3. Automatic Transmit Power Control
The current detector
Q1053-1
(
NJM12904R
) detects the
current of the driver amplifier
Q1016
(
RQA0004PXDQS
)
and final amplifier
Q1012
(
RQA0011DNS
), and converts
the current difference to the voltage difference.
The output from the current detector
Q1053-1
(
NJM12904R
) is compared with the reference voltage
by
Q1053-2
(
NJM12904R
). The output from
Q1053-2
(
NJM12904R
) controls the gate bias of the driver am-
plifier
Q1016
(
RQA0004PXDQS
) and final amplifiers
Q1012
(
RQA0011DNS
).
The reference voltage changes into two levels (Transmit
Power “High” and “Low”) controlled by the Electric Vol-
ume IC
Q1018
(
AK2330
).
3. PLL Frequency Synthesizer
3-1. VCO (Voltage Controlled Oscillator)
While the radio is receiving, the RX VCO
Q1029
(
CPH3910
) generates a programmed frequency between
186.85 and 224.85 MHz as 1st local signal.
While the radio is transmitting, the TX VCO
Q1037
(
2SC4227
) generates a frequency between 136 and 174
MHz.
The output from VCO is amplified by buffer amplifier
Q1026
and
Q1021
(both
2SC5010
). The buffered VCO
is supplied to the 1st mixer
Q1020
(
3SK293
) in case of
the reception. In the transmission, the buffered VCO is
supplied to other buffer amplifier
Q1019
(
2SK3077
), and
then amplified more by
Q1016
(
RQA0004PXDQS
) and
it is put into the final amplifier
Q1012
(
RQA0011DNS
).
A portion of the buffered VCO is fed back to the PLL IC
Q1046
(
AK1541
) to control the VCV voltage.
3-2. Varactor Control Voltage
The tuning voltage (VCV) of VCO is established the lock
range of VCO by controlling the cathode of varactor di-
odes
D1021
,
D1022
,
D1023
, and
D1025
(all
1SV325
)
for receiving, and
D1027
and
D1028
(both
1SV325
) for
transmitting.
3-3. PLL
The PLL IC
Q1046
(
AK1541
) is consists of reference
divider, main divider, phase detector, charge pumps, and
pulse swallow operation.
The reference frequency from TCXO
X1002
(16.8 MHz)
is inputted to pin 10 of PLL IC
Q1046
(
AK1541
) and
is divided by reference divider. On the other hand, the
feedback signal of the VCO inputted to 17 pin of PLL IC
Q1046
(
AK1541
), and is divided with the dividing ratio
which becomes same frequency as the output of reference
divider.
These two signals are compared by phase detector, and
then phase difference pulse is generated. The phase dif-
ference pulse is becomes a DC voltage through the charge
pumps and LPF, and it controls the VCO.
The PLL serial data from CPU
Q1028
(
R5F100LHDFB
)
is sent with three lines of SDO (pin 5), SCK (pin 6) and
PSTB (pin 4).
The lock condition of PLL is output from the UL (pin 7)
terminal of the PLL IC
Q1046
(
AK1541
). The UL termi-
nal becomes “High” at the lock condition, and becomes
“Low” at the unlock condition.
The CPU
Q1028
(
R5F100LHDFB
) is always watch-
ing over the UL condition, and when it becomes “Low”
unlocked condition, the CPU prohibits transmitting and
receiving.
Circuit Description