12
Automatic Transmit Power Control
RF power output from the final amplifier is sampled
by C1265/C1271 and is rectified by
D1039
(
HSM88WA
).
The resulting DC voltage passes through the Automatic
Power Controller
Q1057
(
NJU7012F
) to the APC atten-
uator
D1010
(
RN739F
) and final amplifier
Q1061
(
2SK2974
), so as to control the power output.
Transmit Inhibit
When the transmit PLL is unlocked, pin 14 of PLL
chip
Q1031
(
LV2105V
) goes to a logic “HIGH”. The
resulting DC “unlock” control voltage is switches off TX
inhibit switches
Q1038
(
RT1N241M
),
Q1040
(
2SC4116GR
), and
Q1041
(
DTA143EU
) to disable the
supply voltage to transmitter RF amplifiers
Q1047
, dis-
abling the transmitter.
Spurious Suppression
Generation of spurious products by the transmitter is
minimized by the fundamental carrier frequency being
equal to the final transmitting frequency. Additional har-
monic suppression is provided by a low-pass filter con-
sisting of L1024, L1025 & L1029 and C1260, C1266,
C1267, C1272, C1273 & C1278, resulting in more than
60 dB of harmonic suppression prior to delivery of the
RF signal to the antenna.
PLL Frequency Synthesizer
PLL circuitry consists of VCO
Q1025
(
2SC5226
),
VCO buffer
Q1030
&
Q1039
(both
2SC5226
), and PLL
subsystem IC
Q1031
(
LV2105V
), which contains a ref-
erence divider, serial-to-parallel data latch, programma-
ble divider and phase comparator.
Stability is maintained by a regulated 3.5 V supply via
Q1044
(
2SB1132Q
) and
Q1034
(
S-81235SGUP-DQI
)
which feeds the PLL reference oscillator
Q1045
(
2SC4116GR
), as well as capacitors associated with the
17.475 MHz frequency reference crystal
X1002
.
In the receive mode, VCO
Q1025
oscillates between
153.4 and 172.4 MHz. The VCO output is buffered by
Q1030
and
Q1039
, and applied to the prescaler section
of
Q1031
. There the VCO signal is divided by 64 or 65,
according to a control signal from the data latch section
of
Q1031
, before being applied to the programmable di-
vider section of
Q1031
. The data latch section of
Q1031
also receives serial dividing data from the microproces-
sor
Q1014
(
LC87F72CBA
), which causes the pre-divided
VCO signal to be further divided in the programmable
divider section, depending upon the desired receive fre-
quency, so as to produce a 5 kHz derivative of the current
VCO frequency.
Meanwhile, the reference divider section of
Q1031
divides the 17.475 MHz crystal reference from the refer-
ence oscillator
Q1045
by 3495 to produce the 5 kHz loop
Circuit Description
reference. The 5 kHz signal from the programmable di-
vider (derived from the VCO) and that derived from the
reference oscillator are applied to the phase detector sec-
tion of
Q1031
, which produces a pulsed output with pulse
duration depending on the phase difference between the
input signals. This pulse train is filtered to DC and re-
turned to the varactor
D1011
(
HVU350
).
Changes in the level of the DC voltage applied to the
varactors affect the reactance in the tank circuit of the
VCO, changing the oscillating frequency of the VCO ac-
cording to the phase difference between the signals de-
rived from the VCO and the crystal reference oscillator.
The VCO is thus phase-locked to the crystal reference
oscillator.
The output of the VCO
Q102
5 is buffered by
Q1030
before application to the 1st mixer, as described previously.
For transmission, the VCO
Q1025
oscillates between
118 and 137 MHz. The remainder of the PLL circuitry is
shared with the receiver. However, the dividing data from
the microprocessor is such that the VCO frequency is at
the actual transmit frequency (rather than offset for IFs,
as in the receiving case).
Receive and transmit buses select which VCO is made
a c t i v e b y
Q 1 0 2 1
(
R T 1 N 2 4 1 M
) . F E T
Q 1 0 3 2
(
2SK880GR
) buffers the VCV line for application to the
tracking band-pass filters in the receiver front end.
When the power saving feature is active, the micro-
processor periodically signals to the PLL IC
Q1032
to
conserve power, and to shorten lock-up time.
Push-To Talk Transmit Activation
The
PTT
switch on the microphone is fed through the
PTT controller,
Q1002
(
UMZ2N
), to pin 35 of micropro-
cessor
Q1014
, so that when the PTT switch is closed, pin
88 of
Q1014
goes high. This signals cut off the receiver by
disabling the 5 V supply bus at
Q1019
(
DTA143EU
) which
feeds the front-end, FM IF subsystem IC
Q1052
, and re-
ceiver VCO circuitry. At the same time,
Q1040
(
2SC4116GR
) and
Q1034
(
DTA143EU
) activates the
transmit 5 V supply line to enable the transmitter.
VOR Circuit
When the transceiver is set in the navigation band
(108.000-117.975 MHz), VOR CNTL port (pin 100 of
Q1014
) becomes “Low” turning the 3.5V supply bus
Q1046
(
RT1P441U
) ON, therefore the VOR circuit ON.
A portion of the AF signal form the AM/FM IF sub-
system IC
Q1052
applied to the VOR circuit, consisting
of
Q1053
(
NJM2901V
), and
Q1058
(
NJM2902V
),
where it is detected a variable signal and reference signal
from a VOR station. The VOR circuit sends these signals
to the microprocessor
Q1014
.
