Page 13
www.versitron.com
4.3
FUNCTIONAL DESCRIPTION
The unit consists of the following circuits:
4.3.1
Ring detection
4.3.2
Loop circuit detection circuit
4.3.3
Reverse battery detection circuit
4.3.4
Analog-to-digital conversion
4.3.5
CPLD (Mux / Demux)
4.3.6
RS-485 / RS-422 data transmission circuit
4.3.7
Fiber Optic / Copper transceiver circuit
4.3.1
Ring Detection
The Ring signal from the Central Office (which is normally 65 Vrms to 104 Vrms, with 20Hz ± 3Hz) is
detected by the optocoupler U14 and sent to CPLD, U1 via the D flip-flop U7. When there is no Ring signal,
C20 is charged to +5 and the D flip-flop is cleared.
4.3.2 Loop Current Detection Circuit
The Loop indication signal can be detected only when there is an ON-HOOK condition at the subscriber
side Modem. The current supplied by the central office can vary from 17mA to 25mA. When this condition is
present U13 optocoupler detects the current and discharges C23 (68µF) to trigger the LOOP signal or LED.
4.3.3 Reverse Battery Detection Circuit
Normally Tip is 48VDC with respect to Ring. When this condition is reverse, that is Ring is 48VDC with
respect to Tip, U12 optocoupler detects the condition and triggers the REVBAT signal which turns on the
RBAT LED.
4.3.4 Analog-to-Digital Conversion
A 2W / 4W Hybrid circuit is used before the A/D circuit, this signal is then digitized and band limited for
the digital system. On the reverse path the digital data stream is reconstructed into an analog audio signal. The
sampling rate on the audio signal is 256Khz to ensure signal quality.
4.3.5 CPLD (Mux / Demux)
The CPLD is used to mux
/
demux the digitized audio and RS-485 or RS-422 digital data signal. In
essence, it is an asynchronous-to-synchronous converter encoded using proprietary VHDL programming
designed at VERSITRON. A 20MHz Oscillator, Y1, provides the clock input to the CPLD.
