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Reference

Manual

DOC. REV. 4/7/2008

SPX-2

Sixteen-line Digital I/O Serial

Peripheral Expansion (SPX™)

Board

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Summary of Contents for SPX-2

Page 1: ...Reference Manual DOC REV 4 7 2008 SPX 2 Sixteen line Digital I O Serial Peripheral Expansion SPX Board ...

Page 2: ...cument is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes PC 104 and the PC 104 logo are trademarks of th...

Page 3: ... private spx2support asp contains additional information and resources for this product including Reference Manual PDF format Data sheets and manufacturers links for chips used in this product Utility routines and benchmark software This is a private page for SPX 2 users that can be accessed only be entering this address directly It cannot be reached from the VersaLogic homepage ...

Page 4: ...rge 3 Technical Support 4 Repair Service 4 Physical Details 5 SPX 2 Board Layout 5 Hardware Assembly 6 Connector Functions and Interface Cables 7 Jumper Summary 7 J1 Connector Pinout 7 Digital I O 8 Description 8 External Connections 8 Digital I O Port Configuration 9 Interrupt Generation 9 Writing to a Digital I O Port 9 Base Board SPI Registers 11 SPI Data Registers 13 ...

Page 5: ...nections on SPX boards are provided through screw terminal wire connections All SPX boards are RoHS compliant and industrial temperature rated ABOUT SPI The SPI bus specifies four logic signals SCLK Serial clock output from master MOSI Master output slave input output from master MISO Master input slave output output from slave and SS Slave select output from master The SPI implementation on Versa...

Page 6: ...rating Temperature 40 C to 85 C Power Requirements 5 0V 5 9 0 mA 45 mW typ 155 mA 773 mW max Interface cable provides 500 mA total to be shared by SPX modules Digital I O 16 channel 24 mA outputs 3 3V LVCMOS not 5V tolerant Compatibility SPX Full compliance Any 3 3V signaling SPI interface 8 MHz maximum clock Weight 0 044 lbs 0 020 kg Compliance RoHS Full compliance Specifications are subject to c...

Page 7: ...ropean Union EU beginning July 1 2006 VersaLogic Corporation is committed to supporting customers with high quality products and services meeting the European Union s RoHS directive Warnings ELECTROSTATIC DISCHARGE Electrostatic discharge ESD can damage boards disk drives and other components The circuit board must only be handled at an ESD workstation If an approved station is not available some ...

Page 8: ...n be contact if any questions arise Quantity of items being returned The model and serial number barcode of each item A detailed description of the problem Steps you have taken to resolve or recreate the problem The return shipping address Warranty Repair All parts and labor charges are covered including return shipping charges for UPS Ground delivery to United States addresses Non warranty Repair...

Page 9: ...shows the dimensions of the SPX 2 board as well as the location of connectors jumpers and mounting holes Figure 1 SPX 2 Board Layout Not to scale All dimensions in inches 2 1 5 1 5 1 1 2 3 775 3 375 J1 SPX to Base Board J2 DIO J3 DIO V1 Slave Select 1 0 39 5 1 1 5 J5 DIO J4 DIO ...

Page 10: ...he corner mounting holes These standoffs are secured to the board typically across the PC 104 and PC 104 Plus stack locations using pan head screws Standoffs and screws are available as part number VL HDW 101 Figure 2 SPX Board Mounting Two SPX boards mounted across the PC 104 and PC 104 Plus stack locations ...

Page 11: ...Digital I O Bare wires to 5 pin screw terminal J4 Digital I O Bare wires to 5 pin screw terminal J5 Digital I O Bare wires to 5 pin screw terminal Jumper Summary Table 2 Jumper Summary Jumper Block Description As Shipped V1 1 2 Slave Select 0 In V1 3 4 Slave Select 1 Out V1 5 6 Slave Select 2 Out V1 7 8 Slave Select 3 Out J1 Connector Pinout Table 3 J1 Connector Pinout Pin Signal Name Description ...

Page 12: ...digital I O expander communicates with the host computer through the SPX interface EXTERNAL CONNECTIONS Digital I O channels 0 15 are accessed via connectors J2 through J5 of the SPX 2 as shown in the following table Table 4 Digital I O Connectors J2 Pin Signal Name Description 1 GPA0 Digital I O 0 2 GPA1 Digital I O 1 3 GPA2 Digital I O 2 4 GPA3 Digital I O 3 5 Ground Ground J3 1 GPA4 Digital I O...

Page 13: ... I O chip register settings Please refer to the Microchip MCP23S17 datasheet for more information The base board s EBX 11 and EBX 22 on board digital I O chips must be configured for open drain and mirrored interrupts in order for any SPI device to use hardware interrupts See the base board s reference manual for instructions Note that the SPX 2 interrupts should be configured as mirrored but not ...

Page 14: ...action Write 55h to MCP23S17 register GPIOA MOV DX 1DBh MOV AL 55h SPIDATA1 data to write OUT DX AL MOV DX 1DCh MOV AL 14h SPIDATA2 MCP23S17 register address 14h OUT DX AL MOV DX 1DDh MOV AL 40h SPIDATA3 MCP23S17 write command OUT DX AL CALL BUSY Poll busy flag to wait for SPI transaction BUSY MOV DX 1D9h IN AL DX Get SPISTATUS AND AL 01h Isolate the BUSY flag JNZ BUSY Loop if SPI transaction not ...

Page 15: ...elect modes SPILEN1 SPILEN0 Frame Length 0 0 8 bit 0 1 16 bit 1 0 24 bit 1 1 32 bit D3 MAN_SS SPI Manual Slave Select Mode This bit determines whether the slave select lines are controlled through the user software or are automatically controlled by a write operation to SPIDATA3 1DDh If MAN_SS 0 then the slave select operates automatically if MAN_SS 1 then the slave select line is controlled manua...

Page 16: ...ardware IRQ Enable Enables or disables the use of the selected IRQ IRQSEL by an SPI device 0 SPI IRQ disabled default 1 SPI IRQ enabled Note The selected IRQ is shared with PC 104 ISA bus devices CMOS settings must be configured for the desired ISA IRQ D2 LSBIT_1ST SPI Shift Direction Controls the SPI shift direction of the SPIDATA registers The direction can be shifted toward the least significan...

Page 17: ...l initiate the SPI clock and if the MAN_SS bit 0 will also assert a slave select to begin an SPI bus transaction Increasing frame sizes from 8 bit use the lowest address for the least significant byte of the SPI data word for example the LSB of a 24 bit frame would be SPIDATA1 Data is sent according to the LSBIT_1ST setting When LSBIT_1ST 0 the MSbit of SPIDATA3 is sent first and received data wil...

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