VersaLogic Fox VL-EPM-19 Page 14 Hardware Reference Manual Download | Manualshive

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Introduction

EPM-19 Hardware Reference Manual

5

Dimensions and Mounting

The EPM-19 complies with the PC/104 standard which provides for specific mounting hole and
PC/104-

Plus

stack locations as shown in Figure 5.

Figure 5. EPM-19 Dimensions and Mounting Holes

(Not to scale. All dimensions in inches.)

CAUTION:

The EPM-19 must be supported at all four mounting points to prevent
excessive flexing when expansion modules are attached and removed. Flex
damage caused by excessive force on an improperly mounted circuit board is
not covered under the product warranty.

H

ARDWARE

A

SSEMBLY

The EPM-19 mounts on four hardware standoffs using the corner mounting holes. These
standoffs are secured to the underside of the circuit board using pan head screws.

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Summary of Contents for Fox VL-EPM-19

Page 1: ...Hardware Reference Manual REV 7 13 2017 Fox VL EPM 19 DMP Vortex86DX2 SoC based SBC with dual Ethernet Video USB SATA Counter Timers Mini PCIe microSD GPIO SPX and PC 104 Plus Interface ...

Page 2: ... ensure this document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes PC 104 and the PC 104 logo are t...

Page 3: ...not be reached from the VersaLogic homepage The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with your VersaLogic product VersaTech KnowledgeBase If you have additional questions contact VersaLogic Technical Support at 503 747 2261 VersaLogic support engineers are also available via e mail at Support VersaLogic com REPAIR SERVICE If your product requires service...

Page 4: ...inning July 1 2006 VersaLogic Corporation is committed to supporting customers with high quality products and services meeting the European Union s RoHS directive Cautions ELECTROSTATIC DISCHARGE Electrostatic discharge ESD can damage boards disk drives and other components The circuit board must only be handled at an ESD workstation If an approved station is not available some measure of protecti...

Page 5: ...e on an improperly mounted circuit board is not covered under the product warranty See page 5 for more details EARTH GROUND REQUIREMENT All mounting standoffs should be connected to earth ground chassis ground This provides proper grounding for EMI purposes Figure 1 shows the locations of the board s mounting holes All mounting holes identified in Figure 1 must be connected to earth ground Figure ...

Page 6: ...Clearing CMOS RAM 11 Operating System Installation 12 ACPI Version Setting 12 Windows XP Considerations 12 Linux Considerations 12 Board Features 13 CPU 13 DMA Controller 13 Watchdog Timers 13 Real time Clock 13 Vortex86DX2 SoC On chip Temperature Sensor 14 System RAM 14 I O Interfaces 14 Power Delivery 15 Main Power Connector 15 Cabling 16 Battery Power Options 16 VL CBR 0203 External Battery Mod...

Page 7: ...or 38 Cabling 39 Compatible LVDS Panel Displays 39 BIOS Settings for Boot Display Devices 40 Console Redirection 40 Enabling Synchronous Display Output 41 Network Interfaces 42 Controller Configuration 42 Ethernet Connectors 42 Cabling 43 On Board Ethernet Status LEDs 44 Off Board Ethernet Status LEDs 44 Expansion Interfaces 45 SPX Expansion Bus 45 Cabling 46 VersaLogic SPX Expansion Modules 46 PC...

Page 8: ... Figure 16 Location of the mSATA Activity LED 27 Figure 17 Location of PCIe Mini Card LEDs 28 Figure 18 Location and Pin Orientation of User I O Connector 29 Figure 19 Location and Pin Orientation of Serial Port Connectors 31 Figure 20 COM3 COM4 End point Termination Jumpers 34 Figure 21 VGA Connector Location and Pin Configuration 36 Figure 22 Location of the LVDS Connector 38 Figure 23 Wiring fo...

Page 9: ...Pinout 32 Table 14 Recommended Serial Port Settings for Vortex86DX2 BIOS 33 Table 15 COM3 COM4 Termination Jumpers 34 Table 16 J8 VGA Video Output Pinout 37 Table 17 J15 LVDS Flat Panel Display Connector Pinout 39 Table 18 Compatible LVDS Interface TFT Technology Flat Panel Displays 39 Table 19 BIOS Settings for Boot Display Devices and Corresponding Resolutions 40 Table 20 Ethernet Connector Pino...

Page 10: ...igure 3 shows the connectors and major components on the bottom side of the board Item Description Item Description A PC 104 Plus PCI connector J PC 104 ISA connector B PCIe Minicard mSATA connector K PC 104 ISA connector C Battery L Main power connector D Ethernet port 0 1 connector M SATA connector E COM3 COM4 connector N DRAM devices F COM1 COM2 connector O VGA connector G User I O CBR 4005B ma...

Page 11: ... Figure 3 VL EPM 19 Fox Single Board Computer Bottom Side EPM 19 boards are subjected to 100 functional testing and are backed by a limited five year warranty Careful parts sourcing and US based technical support ensure the highest possible quality reliability service and product longevity for this exceptional SBC ...

Page 12: ...m supported resolution Digital Video output LVDS video output Support for 18 bit or 24 bit single channel LVDS flat panel displays Video BIOS support for 640x480 800x480 800x600 1024x600 and 1024x768 System Reset Vcc sensing resets when the 5V 3 3V 1 8V 1 5V 1 2V or 1 0V power rails vary by more than 10 of their optimal values Ethernet interface Two auto detect 10BaseT 100BaseTX ports COM1 2 inter...

Page 13: ...Introduction EPM 19 Hardware Reference Manual 4 EPM 19 Block Diagram Figure 4 EPM 19 Block Diagram ...

Page 14: ...e All dimensions in inches CAUTION The EPM 19 must be supported at all four mounting points to prevent excessive flexing when expansion modules are attached and removed Flex damage caused by excessive force on an improperly mounted circuit board is not covered under the product warranty HARDWARE ASSEMBLY The EPM 19 mounts on four hardware standoffs using the corner mounting holes These standoffs a...

Page 15: ...FPGA s registers and programming information for the board s hardware interfaces EPM 19_EBX 18 BIOS Reference Manual provides information on accessing and configuring settings in the BIOS Setup utility All BIOS menus submenus and configuration options are described VersaAPI Installation and Reference Guide describes the shared library of API calls for reading and controlling on board devices on ce...

Page 16: ...ndled at an ESD workstation or while wearing a grounded antistatic wrist strap Before you begin unpack the EPM 19 and accessories Verify that you received all the items you ordered Inspect the system visually for any damage that may have occurred in shipping Contact support versalogic com immediately if any items are damaged or missing Gather all the peripheral devices you plan to attach to the EP...

Page 17: ...ower up the system double check all the connections Make sure all cables are oriented correctly and that adequate power will be supplied to the EPM 19 and peripheral devices 4 Power On Turn on the ATX power supply and the video monitor If the system is correctly configured a video signal should soon be present 5 Change BIOS Setup utility settings Enter the BIOS Setup utility by pressing Delete dur...

Page 18: ...Configuration and Setup EPM 19 Hardware Reference Manual 9 Jumper Blocks JUMPERS BLOCKS IN THE AS SHIPPED CONFIGURATION Figure 6 Jumper Block Locations ...

Page 19: ...the Board without a Battery page 19 V4 Battery Saver 1 only or jumper is removed default 1 2 Battery is connected Battery Saver Jumper page 18 BIOS Setup Utility The EPM 19 permits users to modify the BIOS Setup utility defaults Refer to the EPM 19_EBX 18 BIOS Reference Manual available on the EPM 19 Product Support Web Page for information on accessing and configuring settings in the BIOS Setup u...

Page 20: ...ns 2 3 Figure 7 shows the location of the V3 jumper block 3 Leave the jumper in place for at least five seconds 4 Move the jumper to back to its default position connecting pins 1 2 5 Power on the EPM 19 Figure 7 Location of the V3 Clear CMOS Jumper Integrator s Note If clearing the contents of CMOS RAM fails to restore the board to proper operation and you are unable to enter the BIOS Setup utili...

Page 21: ...ETTING The ACPI version will need to be configured in the BIOS Setup utility as follows For Windows 7 set the ACPI version to V3 0 Windows 7 requires version 2 0 or later For Windows XP set the ACPI version to V1 0 Windows XP may function with version 2 0 but has not been fully tested Integrator s Note The EPM 19 board has been tested extensively with Windows 7 and seems to operate reliably with t...

Page 22: ...two controllers and will default to cascade mode as it cannot be used for any other purpose In addition to accepting requests from DMA slaves the DMA controller also responds to requests that are initiated by software The Vortex86DX2 provides the timing control and data size translation for the DMA transfer between memory ISA or DRAM and the ISA bus I O Also the DX2 is ISA compatible with 24 bit a...

Page 23: ...emperature 512 MB 333 MHz EPM 19SBK Standard temperature 1 GB 333 MHz EPM 19EAK Extended temperature 512 MB 300 MHz EPM 19EBK Extended temperature 1 GB 300 MHz I O Interfaces The EPM 19 board s I O interfaces and their associated connectors are described in later chapters as follows Mass Storage Interfaces SATA and microSD beginning on page 22 Multi purpose I O USB PCIe MiniCard mSATA User I O beg...

Page 24: ...tion of the Main Power Connector CAUTION To prevent severe and possibly irreparable damage to the system it is critical that the power connector is wired correctly Make use of all 5 VDC pins and all ground pins to prevent excess voltage drop Note The 3 3 VDC 12 VDC and 12 VDC inputs on the power connector are only required for PC 104 Plus and PC 104 expansion modules that require these voltages ...

Page 25: ...lowing information will be useful EPM 19 Board Connector Mating Connector FCI 78207 110HLF FCI 69176 010LF BATTERY POWER OPTIONS The battery circuit on the EPM 19 provides power for the Real Time Clock RTC and power to store BIOS Setup utility settings in CMOS RAM CAUTION To prevent shorting premature failure or damage to the Lithium battery do not place the board on a conductive surface such as m...

Page 26: ...nnected to the board through the J11 external battery connector Figure 9 shows the location and pin orientation of the external battery connector Figure 9 Location and Pin Orientation of the External Battery Connector VL CBR 0203 EXTERNAL BATTERY MODULE The VL CBR 0203 external battery module is compatible with the EPM 19 For more information contact Sales VersaLogic com Figure 10 VL CBR 0203 Latc...

Page 27: ...is jumper keeps the Lithium battery from discharging keeping it disconnected before the EPM 19 board is in the customer s hands and ready to be used The default configuration of the jumper is a no connect position placed only on pin 1 Figure 11 shows the location of the V4 Battery Saver Jumper Table 6 Battery Saver Jumper Truth Table V4 Jumper Position Condition Pin 1 only default Battery is disco...

Page 28: ...SoC RTC well This is done by removing the V4 jumper leaving pins 1 and 2 unconnected if you want to keep the battery with the product otherwise the on board battery would have to be unsoldered You can store the V4 jumper in its default position connected only to pin 1 3 Make certain there are no other batteries connected to the board that is either attached to the J11 external battery connector or...

Page 29: ...A reset button is provided on the CBR 4005B paddleboard See Figure 27 on page 49 for the location of the reset button on the CBR 4005B paddleboard LEDs Indicators Figure 13 shows the locations of the boards LEDs indicators LED s Description For more information see D10 mSATA activity LED Page 27 D6 D5 PCI Mini Card LEDs Page 28 D3 D8 Ethernet status LEDs Page 44 Figure 13 Locations of the LEDs Ind...

Page 30: ...he CBR 4005B paddleboard See Figure 27 on page 49 for the location of the Programmable LED on the CBR 4005B paddleboard For instructions on how to switch the Programmable LED on and off refer to the EPM 19 Programmer s Reference Manual available on the EPM 19 Product Support Web Page External Speaker A miniature 8 Ω speaker can be connected between user I O connector J9 pin 15 SPKR and J9 pin 13 V...

Page 31: ...s Most current ATX power supplies provide SATA connectors and many SATA drives provide both types of power connectors If the power supply you are using does not provide SATA connectors adapters are available Integrator s Note Only one SATA port is available on the Vortex86DX2 chip so only the J10 SATA port or the J2 mSATA port can be used both cannot be used at the same time Whenever J2 has an mSA...

Page 32: ...SD card with the EPM 19 The microSD card interface is not hot pluggable A microSD card will not be recognized as part of the system if it is not plugged in before power is applied to the board or before a push button reset is applied This is not a limitation of the EPM 19 board it is a limitation of the DX2 chip When a microSD card is inserted at power up the default boot setting is to boot from i...

Page 33: ...while the board is powered on and the OS attempts to access a file on the drive that is the microSD card the results are unpredictable The best case scenario is that the drive drops out as it would in Windows Explorer when running Windows 7 from a SATA drive and using the microSD as an additional hard drive However if Windows does not try to access the microSD card while you have it out and you pu...

Page 34: ...ght PCI Express Mini Card or an mSATA module Note PCIe Mini Cards using small 512 byte or below I O address ranges may not be accessible The PCIe Mini Card interface includes one PCIe x1 lane one hubbed USB 2 0 channel and the SMBus interface The socket is compatible with plug in Wi Fi modems GPS receivers Flash data storage and other cards for added flexibility For more information on PCIe Mini C...

Page 35: ...ta Reserved Not connected 37 GND Ground GND Ground 38 USB_D USB data Reserved Not connected 39 3 3VAUX 3 3V auxiliary source 3 3V 3 3V source 40 GND Ground GND Ground 41 3 3VAUX 3 3V auxiliary source 3 3V 3 3V source 42 LED_WWAN Wireless WAN LED Reserved Not connected 43 GND mSATA detect Note 1 GND NC Ground not connected Note 1 44 LED_WLAN Wireless LAN LED Reserved Not connected 45 NC Not connect...

Page 36: ... signal is non functional as an option for the PCIe Minicard mux selection This signal has a pull down internal to the FPGA to prevent it from floating high which enables it The FPGA default is to use J2 pin 51 as the mux enable signal PRES_DISABLE2 which works with all of our Minicards The result of this condition is that certain combinations of bootable devices may not yield expected results Tab...

Page 37: ...ss PAN Note Yellow Illuminates when the 3 3 V power to the Mini Card is on It alerts users to not hot plug the Mini Card Because the Vortex86DX2 processor does not support sleep modes the power is always on to the PCIe Mini Card socket when the board is powered successfully D5 Green Activity on Wireless WAN Note Yellow Activity on Wireless LAN Note Note These LEDs will illuminate when the associat...

Page 38: ...ly muxed with six timer I O signals per FPGA registers Three LEDs two Ethernet link status LEDs and a programmable LED Power switch Push button reset switch Speaker output This connector uses IEC 61000 4 2 rated TVS components to help protect against ESD damage Figure 18 shows the location and pin orientation of the user I O connector Figure 18 Location and Pin Orientation of User I O Connector ...

Page 39: ... 20 GND 21 Reserved 22 V_BATT 23 Reserved 24 RETURN_BATT 25 GND 26 GND 27 FPGA GPIO1 28 FPGA GPIO2 29 FPGA GPIO3 30 FPGA GPIO4 31 GND 32 GND 33 FPGA GPIO5 34 FPGA GPIO6 35 FPGA GPIO7 36 FPGA GPIO8 37 3 3 V 38 GND 39 ETH0 LED 40 ETH1 LED CABLING An adapter cable part number CBR 4005A is available for connecting the CBR 4005B paddleboard to the EPM 19 This is a 12 inch Pico Clasp 40 pin to 40 pin ca...

Page 40: ...al ports There are no hardware configuration jumpers for COM1 and COM2 because they only operate in RS 232 mode IRQ lines are chosen in the BIOS Setup utility COM3 and COM4 can be operated in RS 232 or RS 422 485 mode IRQ lines are chosen in the BIOS Setup utility Additional non standard baud rates are also available through the BIOS Setup utility Serial Port Connectors Figure 19 shows the locatio...

Page 41: ... Port 1 RTS3 TXD3_P COM3 Vortex86DX2 UART2 2 TXD3 TXD3_N 3 CTS3 RXD3_P 4 RXD3 RXD3_N 5 GND GND 6 RTS4 TXD4_P COM4 Vortex86DX2 UART4 7 TXD4 TXD4_N 8 CTS4 RXD4_P 9 RXD4 RXD4_N 10 GND GND CABLING An adapter cable part number CBR 1014 is available for routing the J7 and J6 signals to 9 pin d sub connectors This is a 12 inch Pico Clasp 10 pin to two 9 pin D sub connector cable If your application requi...

Page 42: ...e I O Address IRQ Vortex86DX2 Serial Port UART COM1 3F8h 4 1 COM2 2F8h 10 9 COM3 3E8h 3 2 COM4 2E8h 11 4 Note COM ports are numbered to match EPM 19 I O connector COM numbering Integrator s Note During verification testing the COM ports displayed data compare errors intermittently while running CPU intensive burn in tests on a moderate to heavily loaded system Since IRQ priorities and small data F...

Page 43: ...RS 422 or RS 485 endpoint station it should be disabled for RS 232 and RS 485 non endpoint receivers Table 15 COM3 COM4 Termination Jumpers Jumper Position Function Jumper In Jumper Out 1 2 COM3 Rx End point Termination RS422 485 Note RS 232 default 3 4 COM4 Rx End point Termination RS422 485 Note RS 232 default Note RS 485 non endpoints do not require termination If receivers are mid line remove ...

Page 44: ...with a BIOS Setup utility option The EPM 19 supports two types of video output VGA and LVDS flat panel display A BIOS Setup utility sub menu Boot Display Device selects which output is enabled through POST The operating system will then take over based on the Graphic Utility CRT or LCD selection If the Boot Display Device selected provides incorrect timing information for an attached LCD panel and...

Page 45: ...l 36 VGA Interface Figure 21 shows the location and pin orientation of the J8 VGA video output connector This connector uses IEC 61000 4 2 rated TVS components to help protect against ESD damage Figure 21 VGA Connector Location and Pin Configuration ...

Page 46: ...Ground 5 8 HSYNC Horizontal sync 13 9 Ground 10 10 VSYNC Vertical sync 14 11 CRT_SCL DDC data clock line 15 12 CRT_SDA DDC serial data line 12 CABLING An adapter cable part number CBR 1204 is available to translate J8 into a standard 15 pin D Sub VGA connector This is a 12 inch 12 pin Pico Clasp to 15 pin VGA cable If your application requires a custom cable the following information will be usefu...

Page 47: ...SYNC VSYNC DE on the four differential data output pairs The BIOS Setup utility provides a sub menu Boot Display Device with several options for standard LVDS Flat Panel types If these options do not match the requirements of the panel you are attempting to use contact Support VersaLogic com for a custom video BIOS Figure 22 shows the location of the LVDS connector The 3 3 V power provided to pins...

Page 48: ...nd 15 LVDSA0 Differential Data 0 16 LVDSA0 Differential Data 0 17 GND Ground 18 GND Ground 19 3 3V Protected power supply 20 3 3V Protected power supply CABLING Several LVDS cables are available from VersaLogic VL CBR 2015 20 inch LVDS Flat Panel cable 24 bit Hirose VL CBR 2016 20 inch LVDS Flat Panel cable 18 bit JAE VL CBR 2017 20 inch LVDS cable 24 bit Hirose COMPATIBLE LVDS PANEL DISPLAYS The ...

Page 49: ...he on board video output by redirecting the console to an available COM port In the BIOS Setup utility the Remote Access Configuration sub menu provides the ability to control console redirection When console redirection is enabled you can access the BIOS Setup utility by typing Ctrl C The default settings for the redirected console are as follows Serial Port Number COM1 Base Address IRQ 3F8h 4 Se...

Page 50: ...cted to J8 and a flat panel display connected to J15 to a VGA only configuration follow these steps 1 Leave both display devices connected 2 Use the BIOS Setup utility to change the Synchronous Display option from Enabled to Disabled Save the changes and exit the BIOS Setup utility 3 Reboot the board and allow the operating system to load A video signal will be present on the VGA during BIOS loadi...

Page 51: ...mented through the LAN9512 USB based device That interface can be configured through your operating system ETHERNET CONNECTORS The J3 connector provides access to the Ethernet ports 0 and 1 This connector uses IEC 61000 4 2 rated TVS components to help protect against ESD damage The Ethernet controller auto detects 10BaseT 100Base TX connectors Figure 24 shows the location and pin orientation of t...

Page 52: ...und B 7 TD0_N Auto Switch 8 TD0_P Auto Switch Port 1 9 ETHB_GNDA Ground A 10 ETHB_GNDA Ground A Port 1 11 RD1_N Auto Switch 12 RD1_P Auto Switch 13 ETHB_GNDB Ground B 14 ETHB_GNDB Ground B 15 TD1_N Auto Switch 16 TD1_P Auto Switch CABLING An adapter cable part number CBR 1604 is available This is a 12 inch 16 pin Click Mate to two RJ 45 connector cables If your application requires a custom cable ...

Page 53: ...le 21 On board Ethernet Status LEDs D3 and D8 LED Color Function Status Green Link activity On Active Ethernet cable connected blinks with activity Off Cable not connected no link or cable is not connected to an active hub Orange Link speed On 100 Mbits s Off 10 Mbits s OFF BOARD ETHERNET STATUS LEDS The signals for the Ethernet status LEDs are routed to the J9 user I O connector which in turn can...

Page 54: ...ion Bus Up to two serial peripheral expansion SPX devices can be attached to the EPM 19 at connector J5 using a CBR 1401 or CBR 1402 cable Figure 26 shows the location and pin orientation of the SPX connector Figure 26 J5 SPX Connector Location and Pin Configuration 9 ...

Page 55: ...n Bus The Vortex86DX2 ISA bus interface is an 8 16 bit ISA device with zero wait state and is available through the Vortex86DX2 SoC s internal ISA to PCI bridge The maximum ISA clock frequency is 33 MHz The AT clock is programmable The SoC generates refresh signals to the ISA interface during the DRAM refresh cycle This means the ISA Refresh signal would be modified with the DRAM refresh rate chan...

Page 56: ... before they can potentially be used on the ISA bus Because ISA IRQ sharing is not supported make sure that any IRQ channel used for an ISA device is not used elsewhere For example if ISA IRQ4 is enabled you must use a different IRQ for COM1 to avoid resource conflicts PC 104 PLUS PCI EXPANSION INTERFACE The EPM 19 supports a full PCI interface for all four slots The Vortex86DX2 SoC does not suppo...

Page 57: ...ystem Resources and Maps Refer to the EPM 19 Programmer s Reference Manual for the following information Memory map IRQ map I O map FPGA register map FPGA register descriptions Programming information for the board s hardware interfaces 10 ...

Page 58: ...rence Manual 49 CBR 4005B Paddleboard CBR 4005B Paddleboard CBR 4005B CONNECTORS AND INDICATORS Figure 27 shows the locations of the connectors and indicators on the CBR 4005B paddleboard Figure 27 CBR 4005B Connectors 11 ...

Page 59: ...onnector Pinout Pin Signal Pin Signal 1 5 V 2 GND 3 USB1_P 4 USB2_P 5 USB1_N 6 USB2_N 7 5V 8 GND 9 USB3_P 10 USB4_P 11 USB3_N 12 USB4_N 13 3 3 V 14 GND 15 SPKR 16 PLED 17 No connect 18 RST_BTN 19 GND 20 GND 21 Reserved 22 V_BATT 23 Reserved 24 V_BATT_RETURN 25 GND 26 GND 27 FPGA GPIO1 28 FPGA GPIO2 29 FPGA GPIO3 30 FPGA GPIO4 31 GND 32 GND 33 FPGA GPIO5 34 FPGA GPIO6 35 FPGA GPIO7 36 FPGA GPIO8 37...

Page 60: ...5B Board Connector Mating Connector Molex 501571 4007 Molex 501189 4010 AUXILIARY I O CONNECTOR Figure 27 shows the location and pin orientation of the auxiliary I O connector Figure 29 Location and Pin Orientation of Auxiliary I O Connector Table 25 Auxiliary I O Connector Pinout Pin Signal Pin Signal 1 Reserved 2 V_BATT 3 Reserved 4 V_BATT_RETURN 5 GND 6 GND 7 FPGA GPIO1 8 FPGA GPIO2 9 FPGA GPIO...

Page 61: ...CBR 4005B Paddleboard EPM 19 Hardware Reference Manual 52 DIMENSIONS AND MOUNTING HOLES Figure 30 CBR 4005B Dimensions and Mounting Holes End of document ...

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